Changes
/* PPI 8255 */
== PPI 8255 ==
=== PPI Port A (Port F4xxh) ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usagein CPC''||''Usage in Aleste''
|-
|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick)||[[PSG]] Databus (Sound/Keyboard/Joystick/Printer, Baudrate/Future Timer, and RTC)
|-
|}
=== PPI Port B (Port F5xxh) ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|}
=== PPI Port C (Port F6xxh) ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|}
=== PPI Control (Port F7xxh) ===
This register has two different functions depending on bit7 of the data written to this register.
See the normal CPCs [[8255]] description for details.