* The Z80 has more registers but has to do pretty much everything with them whilst the 6502 can directly use the first 256 bytes of memory for those jobs.
This shows The 6502 and Z80 exemplify the design fundamental differences between the 6502 what would become known as RISC and Z80CISC architectures. The 6502 focused on efficiencywas designed with a streamlined, using its limited transistor budget for the ALU and fast memory accessminimal instruction set to achieve high execution speed. In contrastThe Z80, on the Z80 neglected these and used other hand, incorporated a larger, more transistors for extra registers and complex instructions. However, these Z80's features, like the alternate register instruction set, register pairs aiming to make assembly programming more accessible and 16-bit stack, make it easier to develop complex softwarecreate more compact programs.
The 6502 comes in a 40-pin DIP package. It has been produced by various manufacturers and used in a wide range of applications, from gaming consoles like the [[Atari 2600|Atari VCS]], [[Atari Lynx]], [[Nintendo Entertainment System]] and [[PC-Engine]] to personal computers like the [[Apple II]], [[BBC Micro]], [[Atari XL]], [[Oric]], [[VIC20]] and [[Commodore 64]].
* bit0 - CF - Carry Flag: 1 on unsigned overflow
|| Flags are affected by most operations.
The BF is bit does not a physical flag implemented in a registeractually exist inside the 6502. It The BF bit only appears on exists in the status flag byte pushed to the stack when . When the P register flags are restored (via PLP or RTI), the BF bit is pushed to itdiscarded.
PHP (Push Processor Status) and PLP (Pull Processor Status) can be used to set or retrieve P directly via the stack.
== Decimal Mode ==
BCD operations are limited to addition and subtraction using the Decimal Mode allows ADC and SBC instructionsto use Binary-Coded Decimal (BCD), where each nibble (4 bits) represents a decimal digit (0-9), instead of binary.
On NMOS, when Decimal Mode is on, the ADC and SBC instructions update NF, VF and ZF based on the binary result before the decimal correction is applied. Only CF is updated correctly. On CMOS, all the flags are updated correctly, at the cost of 1 additional cycle.
== Pipelining ==
The 6502 CPU uses some sort We have to dispel the myth of pipeliningin the 6502. If an instruction does not store data we analyze its operation in memory on its last cyclehalf-cycles, the processor can fetch the opcode of the next we see that instruction while executing the last cycle. This execution is very primitive as the 6502 does not have an instruction cache nor even a prefetch queue. It relies on RAM tightly bound to hold all program informationmemory operations without any overlap between different instructions.
As an exampleEach instruction follows a rigid sequence of steps, with no ability to fetch the next instruction EOR #$FF truly takes 3 cycles:* On while executing the first cycle, current one. This means that the opcode $49 will be fetched* During the second cycle the processor decodes the opcode and fetches the parameter #$FF* On the third cycle, the processor will perform the operation and store the result CPU cannot prefetch opcodes or operands ahead of time in register A, but simultaneously it fetches the opcode for the next instructionway a pipelined architecture would.
This is If we invert our perspective and consider ϕ2 as the first half-cycle and ϕ1 as the second, it becomes evident why pipelining does not exist on the EOR instruction effectively takes only 2 cycles6502.
However, this pipelining only makes sense when looking at full cycles. If we break it down into half-cycles, there's no actual overlap. In fact, it's the other way around. If the previous instruction ends with a memory write, the CPU has to wait for a half-cycle before fetching being able to fetch the next instruction on the next ϕ2 half-cycle.
<br>
== Adressing Modes ==
The 6502 uses only one addressing mode per instruction.
{| class="wikitable"
<br>
== NMOS 6502 Instruction Set Execution Sequence ==
For an instruction to fully execute, the 6502 goes through these key phases in order: #Opcode Fetch#Operand Fetch (if needed)#Memory Read / I/O Read (if needed)#Operation#Memory Write / I/O Write (if needed)#At the end of every instruction, the IRQ (if the interrupt disable flag is clear) and NMI pins are checked. As an example, let M[$42]=$80, M[$43]=$10 and Y= Standard instructions $F1. Then the instruction LDA ($42),Y will execute as follow, with ϕ2 as the first half-cycle and ϕ1 as the second half-cycle:*T0: Fetch opcode $B1 (LDA (zp),Y) from memory then increment PC*T1: Fetch operand byte $42 (zero page pointer address) then increment PC*T2: Get low byte from zero page ($80) then increment the zero page address*T3: Get high byte from next zero page location ($10) then add the Y register value ($F1) to $1080*T4: Garbage fetch from memory address $1071 then handle page boundary crossing (since $1080 + $F1 crosses a page)*T5: Read the value from memory address $1171 into the accumulator then no operation in the last half-cycle <br> == NMOS 6502 Instruction Set ==
Cycles are shown in parenthesis for each opcode. p=1 if page is crossed. t=1 if branch is taken.
=== ALU instructions ===
{| class="wikitable" style="white-space: nowrap;"
! ''No arg'' !! A !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! B !! D !! I !! Z !! C
|-
| ADC || || || 69 (2) || 6D (4) || 7D (4+p) || 79 (4+p) || || 65 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || - || Z || C || A + M + CF → A, CF || Add Memory to Accumulator ADd with Carry
|-
| AND || || || 29 (2) || 2D (4) || 3D (4+p) || 39 (4+p) || || 25 (3) || 35 (4) || || 21 (6) || 31 (5+p) || || N || - || - || - || - || Z || - || A ∧ M → A || "bitwise AND" Memory with Accumulatoraccumulator
|-
| ASL || || 0A (2) || || 0E (6) || 1E (7) || || || 06 (5) || 16 (6) || || || || || N || - || - || - || - || Z || C || CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← 0 || Arithmetic Shift Left
|-
| BCC |CMP | || || |C9 (2) | |CD (4) | |DD (4+p) | |D9 (4+p) | || |C5 (3) | |D5 (4) | || |C1 (6) | || 90 D1 (2+t5+p) || - || - N || - || - || - || - || - Z || Branch on CF = 0 C || A - M || Branch on Carry ClearCoMPare accumulator
|-
| BCS CPX || || || E0 (2) || EC (4) || || || || E4 (3) || || || || || B0 (2+t+p) || - N || - || - || - || - || - Z || - C || Branch on CF = 1 X - M || Branch on Carry SetComPare X register
|-
| BEQ CPY || || || C0 (2) || CC (4) || || || || C4 (3) || || || || || F0 (2+t+p) || - N || - || - || - || - || - Z || - C || Branch on ZF = 1 Y - M || Branch on Result ZeroComPare Y register
|-
| BIT DEC || || || || 2C CE (46) || DE (7) || || || 24 C6 (35) || D6 (6) || || || || || N || V - || - || - || - || Z || - || A ∧ M, M<sub>7</sub> - 1 → NF, M<sub>6</sub> → VF || Test Bits in Memory with AccumulatorDECrement memory
|-
| BMI DEX || CA (2) || || || || || || || || || || || || 30 (2+t+p) || - N || - || - || - || - || - Z || - || Branch on NF = X - 1 → X || Branch on Result MinusDEcrement X
|-
| BNE DEY || 88 (2) || || || || || || || || || || || || D0 (2+t+p) || - N || - || - || - || - || - Z || - || Branch on ZF = 0 Y - 1 → Y || Branch on Result Not ZeroDEcrement Y
|-
| BPL EOR || || || 49 (2) || 4D (4) || 5D (4+p) || 59 (4+p) || || 45 (3) || 55 (4) || || 41 (6) || || 10 51 (2+t5+p) || - || - N || - || - || - || - || Z || - || Branch on NF = 0 A ⊻ M → A || Branch on Result Plusbitwise Exclusive OR
|-
| BRK INC || 00 (7) || || || EE (6) || FE (7) || || || E6 (5) || F6 (6) || || || || || - N || - || 1 - || - || 1 - || - Z || - || PC M + 2↓, [FFFE] → PCL, [FFFF] 1 → PCH M || Force InterruptINCrement memory
|-
| BVC INX || E8 (2) || || || || || || || || || || || || 50 (2+t+p) || - N || - || - || - || - || - Z || - || Branch on VF = 0 X + 1 → X || Branch on Overflow ClearINcrement X
|-
| BVS INY || C8 (2) || || || || || || || || || || || || 70 (2+t+p) || - N || - || - || - || - || - Z || - || Branch on VF = Y + 1 → Y || Branch on Overflow SetINcrement Y
|-
| CLC LSR || 18 || 4A (2) || || 4E (6) || 5E (7) || || || 46 (5) || 56 (6) || || || || || 0 || - || - || - || - || - Z || - C || 0 || → /M<sub>7</sub>...M<sub>0 </sub>/ → CF || Clear Carry FlagLogical Shift Right
|-
| CLD ORA || D8 || || 09 (2) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || 11 (5+p) || || || N || - || - || - || 0 || - || - Z || - || 0 A ∨ M → DF A || Clear Decimal Modebitwise OR with Accumulator
|-
| CLI ROL || 58 || 2A (2) || || 2E (6) || 3E (7) || || || 26 (5) || 36 (6) || || || || || N || - || - || - || - || 0 Z || - || - C || CF ← /M<sub>7</sub>...M<sub>0 → IF </sub>/ ← CF || Clear Interrupt DisableROtate Left
|-
| CLV ROR || B8 || 6A (2) || || 6E (6) || 7E (7) || || || 66 (5) || 76 (6) || || || || || N || - || 0 || - || - || - || - Z || - C || CF → /M<sub>7</sub>...M<sub>0 </sub>/ → VF CF || Clear Overflow FlagROtate Right
|-
| CMP SBC || || || C9 E9 (2) || CD ED (4) || DD FD (4+p) || D9 F9 (4+p) || || C5 E5 (3) || D5 F5 (4) || || C1 E1 (6) || D1 F1 (5+p) || || N || - V || - || - || - || Z || C || A - M - (1 - CF) → A || Compare Memory and AccumulatorSuBtract with Carry|} === Move instructions === {| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2| CPX Mnemonic !! colspan=12|Addressing Modes !! colspan=7| Flags !! rowspan=2|| || E0 (Operation !! rowspan=2) || EC (4) || || || || E4 (3) || || || || || || N || - || - || - || - || Z || C || X - M || Compare Index Register X To MemoryDescription
|-
| CPY || || || C0 ! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! (2$nnnn) || CC !! $nn !! $nn,X !! $nn,Y !! (4$nn,X) || || || || C4 !! (3$nn) || || || || || || ,Y !! rel !! N || - || - || - || - || !! V !! B !! D !! I !! Z || !! C || Y - M || Compare Index Register Y To Memory
|-
| DEC LDA || || A9 (2) || AD (4) || CE BD (64+p) || DE B9 (74+p) || || || C6 A5 (53) || D6 B5 (64) || || A1 (6) || B1 (5+p) || || N || - || - || - || - || Z || - || M - 1 → M A || Decrement Memory By OneLoaD Accumulator
|-
| DEX LDX || CA || A2 (2) || AE (4) || || BE (4+p) || || A6 (3) || || || || B6 (4) || || || || N || - || - || - || - || Z || - || X - 1 M → X || Decrement Index Register LoaD X By Oneregister
|-
| DEY LDY || 88 || A0 (2) || AC (4) || BC (4+p) || || || A4 (3) || || || B4 (4) || || || || || N || - || - || - || - || Z || - || Y - 1 M → Y || Decrement Index Register LoaD Y By Oneregister
|-
| EOR PHA || 48 (3) || || 49 (2) || 4D (4) || 5D (4+p) || 59 (4+p) || || 45 (3) || 55 (4) || || 41 (6) || 51 (5+p) || - || N - || - || - || - || - || Z || - || A ⊻ M → A A↓ || "Exclusive OR" Memory with PusH Accumulator
|-
| INC PHP || 08 (3) || || || EE (6) || FE (7) || || || E6 (5) || F6 (6) || || || || - || N - || - 1 || - || - || - || Z || - || M + 1 → M P↓ || Increment Memory By OnePusH Processor status
|-
| INX PLA || E8 68 (24) || || || || || || || || || || || || || N || - || - || - || - || Z || - || X + 1 (S)↑ → X A || Increment Index Register X By OnePuLl Accumulator
|-
| INY PLP || C8 28 (24) || || || || || || || || || || || || || N || - V || - || - D || - I || Z || - C || Y + 1 (S)↑ → Y P || Increment Index Register Y By OnePuLl Processor status
|-
| JMP STA || || || 8D (4) || 4C 9D (35) || 99 (5) || || 6C 85 (53) || 95 (4) || || 81 (6) || || 91 (6) || || - || - || - || - || - || - || - || [PC + 1] → PCL, [PC + 2] A → PCH M || JumpSTore Accumulator
|-
| JSR STX || || || || 20 8E (64) || || || || 86 (3) || || 96 (4) || || || || - || - || - || - || - || - || - || PC + 2↓, [PC + 1] → PCL, [PC + 2] X → PCH M || Jump To SubroutineSTore X register
|-
| LDA STY || || || A9 (2) || AD 8C (4) || BD (4+p) || B9 (4+p) || || A5 84 (3) || B5 94 (4) || || A1 (6) || B1 (5+p) || || N - || - || - || - || - || Z - || - || M Y → A M || Load Accumulator with MemorySTore Y register
|-
| LDX TAX || || || A2 AA (2) || AE (4) || || BE (4+p) || || A6 (3) || || B6 (4) || || || || || N || - || - || - || - || Z || - || M A → X || Load Index Register Transfer A to X From Memory
|-
| LDY TAY || || || A0 A8 (2) || AC (4) || BC (4+p) || || || A4 (3) || B4 (4) || || || || || || N || - || - || - || - || Z || - || M A → Y || Load Index Register Transfer A to Y From Memory
|-
| LSR TSX || || 4A BA (2) || || 4E (6) || 5E (7) || || || 46 (5) || 56 (6) || || || || || 0 N || - || - || - || - || Z || C - || 0 → /M<sub>7</sub>...M<sub>0</sub>/ S → CF X || Logical Shift RightTransfer Stack pointer to X
|-
| NOP TXA || EA 8A (2) || || || || || || || || || || || || N || - || - || - || - || - || - Z || - || No operation X → A || No OperationTransfer X to A
|-
| ORA TXS || || || 09 9A (2) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || 11 (5+p) || || N || - || - || - || - || Z - || - || - || A ∨ M X → A S || "OR" Memory with AccumulatorTransfer X to Stack pointer
|-
| PHA TYA || 48 98 (32) || || || || || || || || || || || || N || - || - || - || - || - Z || - || - Y → A || A↓ Transfer Y to A|} === Jump and Flag instructions === {| Push Accumulator On Stackclass="wikitable" style="white-space: nowrap;"
|-
! rowspan=2| PHP Mnemonic !! colspan=12|Addressing Modes !! colspan=7| 08 (3) Flags !! rowspan=2|Operation !! rowspan=2| || || || || || || || || || || || || - || - || 1 || - || - || - || - || P↓ || Push Processor Status on StackDescription
|-
| PLA || 68 ! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! (4$nnnn) || || || || || || || || || || || || || N || - || - || - || - || Z || - || !! $nn !! $nn,X !! $nn,Y !! (S$nn,X)↑ → A || Pull Accumulator From Stack!! ($nn),Y !! rel !! N !! V !! B !! D !! I !! Z !! C
|-
| PLP BCC || 28 (4) || || || || || || || || || || || 90 (2+t+p) || - || N - || V - || - || D - || I - || Z - || C || (S)↑ → P Branch on CF = 0 || Pull Processor Status From StackBranch on Carry Clear
|-
| ROL BCS || || 2A (2) || || 2E (6) || 3E (7) || || || 26 (5) || 36 (6) || || || B0 (2+t+p) || - || N - || - || - || - || - || Z || C - || Branch on CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← CF = 1 || Rotate One Bit Left (Memory or Accumulator)Branch on Carry Set
|-
| ROR BEQ || || 6A (2) || || 6E (6) || 7E (7) || || || 66 (5) || 76 (6) || || || F0 (2+t+p) || - || N - || - || - || - || - || Z - || C Branch on ZF = 1 || CF → /M<sub>7</sub>...M<sub>0</sub>/ → CF || Rotate One Bit Right (Memory or Accumulator)Branch on EQual
|-
| RTI || 40 (6) BIT || || || 2C (4) || || || || 24 (3) || || || || || || N || V || - || D - || I - || Z || C - || (S)↑ → PA ∧ M, (S)↑ M<sub>7</sub> → PCLNF, (S)↑ M<sub>6</sub> → PCH VF || Return From Interrupttest BITs
|-
| RTS || 60 (6) BMI || || || || || || || || || || || || 30 (2+t+p) || - || - || - || - || - || - || - || (S)↑ → PCL, (S)↑ → PCH, PC + Branch on NF = 1 → PC || Return From SubroutineBranch on MInus
|-
| SBC BNE || || || E9 (2) || ED (4) || FD (4+p) || F9 (4+p) || || E5 (3) || F5 (4) || || E1 (6) || F1 D0 (52+t+p) || - || N - || V - || - || - || - || Z - || C || A - M - (1 - CF) → A Branch on ZF = 0 || Subtract Memory from Accumulator with BorrowBranch on Not Equal
|-
| SEC BPL || 38 (2) || || || || || || || || || || || 10 (2+t+p) || - || - || - || - || - || - || - || 1 || 1 → CF Branch on NF = 0 || Set Carry FlagBranch on PLus
|-
| SED BRK || F8 00 (27) || || || || || || || || || || || || - || - || - 1 || - || 1 || - || - || - || 1 PC + 2↓, [FFFE] → PCL, [FFFF] → DF PCH || Set Decimal ModeBReaK
|-
| SEI BVC || 78 (2) || || || || || || || || || || || 50 (2+t+p) || - || - || - || - || - || 1 || - || - || 1 → IF Branch on VF = 0 || Set Interrupt DisableBranch on oVerflow Clear
|-
| STA BVS || || || || 8D (4) || 9D (5) || 99 (5) || || 85 (3) || 95 (4) || || 81 (6) || 91 70 (62+t+p) || || - || - || - || - || - || - || - || A → M Branch on VF = 1 || Store Accumulator in MemoryBranch on oVerflow Set
|-
| STX CLC || 18 (2) || || || 8E (4) || || || || 86 (3) || || 96 (4) || || || || - || - || - || - || - || - || - 0 || X 0 → M CF || Store Index X in MemoryCLear Carry flag
|-
| STY CLD || D8 (2) || || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || - || - || - || - 0 || - || - || - || Y 0 → M DF || Store Index Y in MemoryCLear Decimal flag
|-
| TAX CLI || AA 58 (2) || || || || || || || || || || || || - || N - || - || - || - 0 || - || Z || - || A 0 → X IF || Transfer Accumulator to Index XCLear Interrupt flag
|-
| TAY CLV || A8 B8 (2) || || || || || || || || || || || || - || N 0 || - || - || - || - || Z || - || A 0 → Y VF || Transfer Accumulator to Index YCLear oVerflow flag
|-
| TSX JMP || BA (2) || || 4C (3) || || || 6C (5) || || || || || || || - || N - || - || - || - || - || Z || - || S [PC + 1] → PCL, [PC + 2] → X PCH || Transfer Stack Pointer to Index XJuMP
|-
| TXA JSR || 8A (2) || || 20 (6) || || || || || || || || || || - || N - || - || - || - || - || Z || - || X PC + 2↓, [PC + 1] → PCL, [PC + 2] → A PCH || Transfer Index X Jump to AccumulatorSubRoutine
|-
| TXS NOP || 9A EA (2) || || || || || || || || || || || || || - || - || - || - || - || - || - || X → S No operation || Transfer Index X to Stack PointerNo OPeration
|-
| TYA RTI || 98 40 (6) || || || || || || || || || || || || N || V || - || D || I || Z || C || (S)↑ → P, (S)↑ → PCL, (S)↑ → PCH || ReTurn from Interrupt|-| RTS || 60 (6) || || || || || || || || || || || || - || - || - || - || - || - || - || (S)↑ → PCL, (S)↑ → PCH, PC + 1 → PC || ReTurn from Subroutine|-| SEC || 38 (2) || || || || || || || || || || || || - || N - || - || - || - || - || Z 1 || 1 → CF || SEt Carry flag|-| SED || F8 (2) || || || || || || || || || || || || - || - || - || 1 || - || - || - || 1 → DF || SEt Decimal flag|-| SEI || 78 (2) || || || || || || || || || || || || - || - || - || - || 1 || - || - || Y 1 → A IF || Transfer Index Y to AccumulatorSEt Interrupt flag
|}
=== Illegal instructions ===
Opcodes in red are unstable. Only 2 A lot of those 7 opcodes ($8Bthese illegal instructions involve a bitwise AND operation, $AB) are actually unstable in the sense that they may produce which is a truly unpredictable resultside effect of the open-drain behavior of NMOS logic. The other 5 opcodes actually produce predictable results – but When two instructions put a value on the conditions under which they do that and bus at the produced results are same time, this creates a bit unexpectedbus conflict resulting effectively in an AND operation. The lower voltage wins because transistors can pull down stronger than resistors can pull up.
{| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2|Mnemonic !! rowspan=2|Combines !! colspan=10|Addressing Modes !! colspan=7|Flags !! rowspan=2|Operation !! rowspan=2|Description
|-
! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! N !! V !! B !! D !! I !! Z !! C
|-
| ANC ALR (ANC2ASR) || AND + ASL/ROL || || 0B, 2B 4B (2) || || || || || || || || || N 0 || - || - || - || - || Z || C || A ∧ M → AAND oper, NF → 0 -> [76543210] -> CF || "AND" Memory with Accumulator then Move Negative Flag to Carry Flagoper + LSR
|-
| ARR || AND + ROR ANC || || 6B 0B (2) || || || || || || || || || N || V - || - || - || - || Z || C || A AND oper, bit(A ∧ M7) / 2 → A -> CF || "AND" Accumulator then Rotate Rightoper + set CF as ASL
|-
| ASR (ALR) || AND + LSR ANC2 || || 4B 2B (2) || || || || || || || || || 0 N || - || - || - || - || Z || C || A AND oper, bit(A ∧ M7) / 2 → A -> CF || "AND" then Logical Shift Rightoper + set CF as ROL
|-
| DCP ANE (DCMXAA) || DEC || style="color: #CC0000;"|'''8B''' (2) || || || || || || || || || N || - || - || - || - || Z || - || (A OR magic) AND X AND oper -> A || * AND X + CMP AND operhighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Turrican 3 on C64 requires a different magic constant than $EE for ANE. $EF is recommended by Groepaz (VICE team)|-| ARR || || 6B (2) || || || || || || || || || N || V || - || - || - || Z || C || A AND oper, CF -> [76543210] -> CF || AND oper + ROR|-| DCP (DCM) || || || CF (6) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || N || - || - || - || - || Z || C || M - 1 → -> M, A - M || Decrement Memory By One then Compare with AccumulatorDEC oper + CMP oper
|-
| ISC (ISB, INS) || INC + SBC || || || EF (6) || FF (7) || FB (7) || E7 (5) || F7 (6) || || E3 (8) || F3 (8) || N || V || - || - || - || Z || C || M + 1 → -> M, A - M → - CF -> A || Increment Memory By One then INC oper + SBC then Subtract Memory from Accumulator with Borrowoper
|-
| JAM (KIL, HLT) || || 02, 12, 22,
32, 42, 52,
B2, D2, F2 (X)
|| || || || || || || || || || - || - || - || - || - || - || - || Stop execution || Halt the CPU. The processor will be trapped infinitely in T1 phase with $FF on the data bus. Reset required.
|-
| LAS (LAR) || STA/TXS + LDA/STX || || || || || BB (4+p) || || || || || || N || - || - || - || - || Z || - || M ∧ S → AND SP -> A, X, S SP || "AND" Memory with Stack PointerLDA/TSX oper
|-
| LAX (LXA) || LDA + LDX || || style="color: #CC0000;"|'''AB''' (2) || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || - || Z || - || M → -> A, -> X || Load Accumulator and Index Register X From MemoryLDA oper + LDX oper
|-
| LXA (LAX) || || style="color: #CC0000;"|'''AB''' (2) || || || || || || || || || N || - || - || - || - || Z || - || (A OR magic) AND oper -> A -> X || Store * AND oper in A and Xhighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Wizball on C64 requires a $EE magic constant for LXA|-| NOP (DOP, TOP) || || 1A, 3A, 5A,
7A, DA, FA (2)
|| 80, 82, 89,
|| || || || - || - || - || - || - || - || - || No operation || No Operation
|-
| RLA || ROL + AND || || || 2F (6) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || 33 (8) || N || - || - || - || - || Z || C || M = CF ← /M7...M0/ ← <- [76543210] <- CF, A ∧ AND M → -> A || Rotate Left then "ROL oper + AND" with Accumulatoroper
|-
| RRA || ROR + ADC || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || - || Z || C || M = CF → /M7...M0/ → -> [76543210] -> CF, A + M + CF → -> A , CF || Rotate Right and Add Memory to AccumulatorROR oper + ADC oper
|-
| SAX (AXS, AAX) || STA + STX || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || - || A ∧ AND X → -> M || Store Accumulator "Stores the bitwise AND" Index Register of A and X in Memory
|-
| SBC SBX (USBCAXS, SAX) || SBC + NOP || || EB CB (2) || || || || || || || || || N || V - || - || - || - || Z || C || (A AND X) - M oper - ~CF → A > X || Subtract Memory from Accumulator with BorrowCMP and DEX at once, sets flags like CMP
|-
| SBX SHA (AXSAHX, SAXAXA) || CMP + DEX || || CB (2) || || style="color: #CC0000;"|'''9F''' (5) | || || || || |style="color: #CC0000;"| '''93''' (6) || N - || - || - || - || - || Z - || C - || (A ∧ AND XAND (H+1) - > M → X || Subtract Memory from Accumulator "Stores A AND" Index Register XAND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SHA SHX (AHXA11, AXASXA, XAS) || STA/STX/STY || || || || || style="color: #CC0000;"|'''9F9E''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || - || A ∧ X ∧ V → AND (H+1) -> M || Store Accumulator "AND" Index Register Stores X "AND" Value(high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SHS SHY (TASSYA, XASSAY) || STA/TXS + LDA/TSX || || || || || style="color: #CC0000;"|'''9B9C''' (5) || || || || || || || - || - || - || - || - || - || - || A ∧ X → S, S ∧ Y AND (H + 1) → -> M || Transfer Accumulator "Stores Y AND" Index Register X to Stack Pointer then Store Stack Pointer "AND" Hi(high-Byte In Memorybyte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SHX SLO (SXA, XASASO) || STA/STX/STY || || 0F (6) || 1F (7) || 1B (7) || style="color: #CC0000;"|'''9E''' 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || - || - Z || - C || M = CF <- || X ∧ (H + 1) → [76543210] <- 0, A OR M -> A || Store Index Register X "AND" ValueASL oper + ORA oper
|-
| SHY SRE (SYA, SAYLSE) || STA/STX/STY || || 4F (6) || 5F (7) || style="color: #CC0000;"5B (7) ||'''9C''' 47 (5) || 57 (6) || || 43 (8) || 53 (8) || || N || - || - || - || - || - Z || - C || M = 0 - || Y ∧ (H + 1) → > [76543210] -> CF, A EOR M -> A || Store Index Register Y "AND" ValueLSR oper + EOR oper
|-
| SLO TAS (ASOXAS, SHS) || ASL + ORA || || || 0F (6) || 1F (7) |style="color: #CC0000;"| 1B '''9B''' (75) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N - || - || - || - || - || Z - || C - || M * 2 → MA AND X -> SP, A ∨ AND X AND (H+1) -> M → A || Arithmetic Shift Left then "OR" Memory with AccumulatorPuts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SRE USBC (LSESBC) || LSR + EOR || EB (2) || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - V || - || - || - || Z || C || M / 2 → M, A ⊻ - M → A || Logical Shift Right then "Exclusive OR" Memory with Accumulator|-| XAA (ANE) || TXA + AND || || style="color: #CC0000;"|'''8B''' (2) || || || || || || || || || N || ~CF - || - || - || - || Z || - || (A ∨ V) ∧ X ∧ M → > A || Non-deterministic Operation of Accumulator, Index Register X, Memory and Bus ContentsSBC oper + NOP
|}
Opcodes in red are unstable.
<br>
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 00 || BRK
|-
| 04 xx || '''NOP ''zpg'''''
|-
| 08 || PHP
|-
| 0C xx xx || '''NOP ''abs'''''
|-
| 10 xx || BPL ''rel''
|-
| 14 xx || '''NOP ''zpg'',X'''
|-
| 18 || CLC
|-
| 1C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 20 xx xx || JSR ''abs''
|-
| 24 xx || BIT ''zpg''
|-
| 28 || PLP
|-
| 2C xx xx || BIT ''abs''
|-
| 30 xx || BMI ''rel''
|-
| 34 xx || '''NOP ''zpg'',X'''
|-
| 38 || SEC
|-
| 3C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 40 || RTI
|-
| 44 xx || '''NOP ''zpg'''''
|-
| 48 || PHA
|-
| 4C xx xx || JMP ''abs''
|-
| 50 xx || BVC ''rel''
|-
| 54 xx || '''NOP ''zpg'',X'''
|-
| 58 || CLI
|-
| 5C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 60 || RTS
|-
| 64 xx || '''NOP ''zpg'''''
|-
| 68 || PLA
|-
| 6C xx || JMP ''zpg''
|-
| 70 xx || BVS ''rel''
|-
| 74 xx || '''NOP ''zpg'',X'''
|-
| 78 || SEI
|-
| 7C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 80 xx || '''NOP #'''
|-
| 84 xx || STY ''zpg''
|-
| 88 || DEY
|-
| 8C xx xx || STY ''abs''
|-
| 90 xx || BCC ''rel''
|-
| 94 xx || STY ''zpg'',X
|-
| 98 || TYA
|-
| 9C xx xx ||style="color: #CC0000;"|'''SHY ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A0 xx || LDY #
|-
| A4 xx || LDY ''zpg''
|-
| A8 || TAY
|-
| AC xx xx || LDY ''abs''
|-
| B0 xx || BCS ''rel''
|-
| B4 xx || LDY ''zpg'',X
|-
| B8 || CLV
|-
| BC xx xx || LDY ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C0 xx || CPY #
|-
| C4 xx || CPY ''zpg''
|-
| C8 || INY
|-
| CC xx xx || CPY ''abs''
|-
| D0 xx || BNE ''rel''
|-
| D4 xx || '''NOP ''zpg'',X'''
|-
| D8 || CLD
|-
| DC xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E0 xx || CPX #
|-
| E4 xx || CPX ''zpg''
|-
| E8 || INX
|-
| EC xx xx || CPX ''abs''
|-
| F0 xx || BEQ ''rel''
|-
| F4 xx || '''NOP ''zpg'',X'''
|-
| F8 || SED
|-
| FC xx xx || '''NOP ''abs'',X'''
|}
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 01 xx || ORA (''zpg'',X)
|-
| 05 xx || ORA ''zpg''
|-
| 09 xx || ORA #
|-
| 0D xx xx || ORA ''abs''
|-
| 11 xx || ORA (''zpg''),Y
|-
| 15 xx || ORA ''zpg'',X
|-
| 19 xx xx || ORA ''abs'',Y
|-
| 1D xx xx || ORA ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 21 xx || AND (''zpg'',X)
|-
| 25 xx || AND ''zpg''
|-
| 29 xx || AND #
|-
| 2D xx xx || AND ''abs''
|-
| 31 xx || AND (''zpg''),Y
|-
| 35 xx || AND ''zpg'',X
|-
| 39 xx xx || AND ''abs'',Y
|-
| 3D xx xx || AND ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 41 xx || EOR (''zpg'',X)
|-
| 45 xx || EOR ''zpg''
|-
| 49 xx || EOR #
|-
| 4D xx xx || EOR ''abs''
|-
| 51 xx || EOR (''zpg''),Y
|-
| 55 xx || EOR ''zpg'',X
|-
| 59 xx xx || EOR ''abs'',Y
|-
| 5D xx xx || EOR ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 61 xx || ADC (''zpg'',X)
|-
| 65 xx || ADC ''zpg''
|-
| 69 xx || ADC #
|-
| 6D xx xx || ADC ''abs''
|-
| 71 xx || ADC (''zpg''),Y
|-
| 75 xx || ADC ''zpg'',X
|-
| 79 xx xx || ADC ''abs'',Y
|-
| 7D xx xx || ADC ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 81 xx || STA (''zpg'',X)
|-
| 85 xx || STA ''zpg''
|-
| 89 xx || '''NOP #'''
|-
| 8D xx xx || STA ''abs''
|-
| 91 xx || STA (''zpg''),Y
|-
| 95 xx || STA ''zpg'',X
|-
| 99 xx xx || STA ''abs'',Y
|-
| 9D xx xx || STA ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A1 xx || LDA (''zpg'',X)
|-
| A5 xx || LDA ''zpg''
|-
| A9 xx || LDA #
|-
| AD xx xx || LDA ''abs''
|-
| B1 xx || LDA (''zpg''),Y
|-
| B5 xx || LDA ''zpg'',X
|-
| B9 xx xx || LDA ''abs'',Y
|-
| BD xx xx || LDA ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C1 xx || CMP (''zpg'',X)
|-
| C5 xx || CMP ''zpg''
|-
| C9 xx || CMP #
|-
| CD xx xx || CMP ''abs''
|-
| D1 xx || CMP (''zpg''),Y
|-
| D5 xx || CMP ''zpg'',X
|-
| D9 xx xx|| CMP ''abs'',Y
|-
| DD xx xx || CMP ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E1 xx || SBC (''zpg'',X)
|-
| E5 xx || SBC ''zpg''
|-
| E9 xx || SBC #
|-
| ED xx xx || SBC ''abs''
|-
| F1 xx || SBC (''zpg''),Y
|-
| F5 xx || SBC ''zpg'',X
|-
| F9 xx xx || SBC ''abs'',Y
|-
| FD xx xx || SBC ''abs'',X
|}
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 02 || '''JAM'''
|-
| 06 xx || ASL ''zpg''
|-
| 0A || ASL A
|-
| 0E xx xx || ASL ''abs''
|-
| 12 || '''JAM'''
|-
| 16 xx || ASL ''zpg'',X
|-
| 1A || '''NOP'''
|-
| 1E xx xx || ASL ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 22 || '''JAM'''
|-
| 26 xx || ROL ''zpg''
|-
| 2A || ROL A
|-
| 2E xx xx || ROL ''abs''
|-
| 32 || '''JAM'''
|-
| 36 xx || ROL ''zpg'',X
|-
| 3A || '''NOP'''
|-
| 3E xx xx || ROL ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 42 || '''JAM'''
|-
| 46 xx || LSR ''zpg''
|-
| 4A || LSR A
|-
| 4E xx xx || LSR ''abs''
|-
| 52 || '''JAM'''
|-
| 56 xx || LSR ''zpg'',X
|-
| 5A || '''NOP'''
|-
| 5E xx xx || LSR ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 62 || '''JAM'''
|-
| 66 xx || ROR ''zpg''
|-
| 6A || ROR A
|-
| 6E xx xx || ROR ''abs''
|-
| 72 || '''JAM'''
|-
| 76 xx || ROR ''zpg'',X
|-
| 7A || '''NOP'''
|-
| 7E xx xx || ROR ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 82 xx || '''NOP #'''
|-
| 86 xx || STX ''zpg''
|-
| 8A || TXA
|-
| 8E xx xx || STX ''abs''
|-
| 92 || '''JAM'''
|-
| 96 xx || STX ''zpg'',Y
|-
| 9A || TXS
|-
| 9E xx xx ||style="color: #CC0000;"|'''SHX ''abs'',Y'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A2 xx || LDX #
|-
| A6 xx || LDX ''zpg''
|-
| AA || TAX
|-
| AE xx xx || LDX ''abs''
|-
| B2 || '''JAM'''
|-
| B6 xx || LDX ''zpg'',Y
|-
| BA || TSX
|-
| BE xx xx || LDX ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C2 xx || '''NOP #'''
|-
| C6 xx || DEC ''zpg''
|-
| CA || DEX
|-
| CE xx xx || DEC ''abs''
|-
| D2 || '''JAM'''
|-
| D6 xx || DEC ''zpg'',X
|-
| DA || '''NOP'''
|-
| DE xx xx || DEC ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E2 xx || '''NOP #'''
|-
| E6 xx || INC ''zpg''
|-
| EA || NOP
|-
| EE xx xx || INC ''abs''
|-
| F2 || '''JAM'''
|-
| F6 xx || INC ''zpg'',X
|-
| FA || '''NOP'''
|-
| FE xx xx || INC ''abs'',X
|}
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 03 xx || '''SLO (''zpg'',X)'''
|-
| 07 xx || '''SLO ''zpg'''''
|-
| 0B xx || '''ANC #'''
|-
| 0F xx xx || '''SLO ''abs'''''
|-
| 13 xx || '''SLO (''zpg''),Y'''
|-
| 17 xx || '''SLO ''zpg'',X'''
|-
| 1B xx xx || '''SLO ''abs'',Y'''
|-
| 1F xx xx || '''SLO ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 23 xx || '''RLA (''zpg'',X)'''
|-
| 27 xx || '''RLA ''zpg'''''
|-
| 2B xx || '''ANC #'''
|-
| 2F xx xx || '''RLA ''abs'''''
|-
| 33 xx || '''RLA (''zpg''),Y'''
|-
| 37 xx || '''RLA ''zpg'',X'''
|-
| 3B xx xx || '''RLA ''abs'',Y'''
|-
| 3F xx xx || '''RLA ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 43 xx || '''SRE (''zpg'',X)'''
|-
| 47 xx || '''SRE ''zpg'''''
|-
| 4B xx || '''ASR #'''
|-
| 4F xx xx || '''SRE ''abs'''''
|-
| 53 xx || '''SRE (''zpg''),Y'''
|-
| 57 xx || '''SRE ''zpg'',X'''
|-
| 5B xx xx || '''SRE ''abs'',Y'''
|-
| 5F xx xx|| '''SRE ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 63 xx || '''RRA (''zpg'',X)'''
|-
| 67 xx || '''RRA ''zpg'''''
|-
| 6B xx || '''ARR #'''
|-
| 6F xx xx || '''RRA ''abs'''''
|-
| 73 xx || '''RRA (''zpg''),Y'''
|-
| 77 xx || '''RRA ''zpg'',X'''
|-
| 7B xx xx || '''RRA ''abs'',Y'''
|-
| 7F xx xx || '''RRA ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 83 xx || '''SAX (''zpg'',X)'''
|-
| 87 xx || '''SAX ''zpg'''''
|-
| 8B xx ||style="color: #CC0000;"|'''XAA ANE #'''
|-
| 8F xx xx || '''SAX ''abs'''''
|-
| 93 xx ||style="color: #CC0000;"|'''SHA (''zpg''),Y'''
|-
| 97 xx || '''SAX ''zpg'',Y'''
|-
| 9B xx xx ||style="color: #CC0000;"|'''SHS TAS ''abs'',Y'''
|-
| 9F xx xx ||style="color: #CC0000;"|'''SHA ''abs'',Y'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A3 xx || '''LAX (''zpg'',X)'''
|-
| A7 xx || '''LAX ''zpg'''''
|-
| AB xx ||style="color: #CC0000;"|'''LXA #'''
|-
| AF xx xx || '''LAX ''abs'''''
|-
| B3 xx || '''LAX (''zpg''),Y'''
|-
| B7 xx || '''LAX ''zpg'',Y'''
|-
| BB xx xx || '''LAS ''abs'',Y'''
|-
| BF xx xx || '''LAX ''abs'',Y'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C3 xx || '''DCP (''zpg'',X)'''
|-
| C7 xx || '''DCP ''zpg'''''
|-
| CB xx || '''SBX #'''
|-
| CF xx xx || '''DCP ''abs'''''
|-
| D3 xx || '''DCP (''zpg''),Y'''
|-
| D7 xx || '''DCP ''zpg'',X'''
|-
| DB xx xx || '''DCP ''abs'',Y'''
|-
| DF xx xx || '''DCP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E3 xx || '''ISC (''zpg'',X)'''
|-
| E7 xx || '''ISC ''zpg'''''
|-
| EB xx || '''SBC USBC #'''
|-
| EF xx xx || '''ISC ''abs'''''
|-
| F3 xx || '''ISC (''zpg''),Y'''
|-
| F7 xx || '''ISC ''zpg'',X'''
|-
| FB xx xx || '''ISC ''abs'',Y'''
|-
| FF xx xx || '''ISC ''abs'',X'''
|}
|}
Opcodes in bold are illegal. Opcodes in red are unstable.
Any instruction xxxxxx11 will execute the instructions at xxxxxx01 and xxxxxx10 at once, using the address mode of the instruction at xxxxxx01.
For example, "SAX abs” ($8F) is the composite of “STA abs” ($8D) and “STX abs” ($8E).
<br>
* On NMOS, an indirect JMP will behave unexpectedly when the indirect address crosses a page boundary, because the 6502 does not add the carry to calculate the address of the high byte. For example, JMP ($19FF) will use the contents of $19FF and $1900 for the JMP address. On CMOS, this issue was fixed, at the cost of 1 additional cycle. In our example, JMP ($19FF) will use the contents of $19FF and $2000 for the JMP address.
* Some instructions, particularly those involving branches or indexed addressing modes, incur an extra cycle if the processor has to cross a memory page boundary. This is problematic for time-sensitive code.
* Conditional jumps are only 8-bit relative. And unconditional jumps are only 16-bit absolute.
* the Z80 pre-decrements on PUSH and post-increments on POP, while the 6502 post-decrements on PHA and pre-increments on PLA, making them behave in opposite ways.
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
* The CLV (Clear Overflow Flag) instruction exist but not the SEV (Set Overflow Flag) instruction.
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.
* The alternate NOPs are not created equal. Some have one- or two-byte operands (which they don't do anything with), and they take different amounts of time to execute.
<br>
== Compared behaviour ==
* The 6502’s Decimal (BCD) mode automatically adjusts ADC and SBC results, while the Z80 requires a DAA instruction after each BCD addition and subtraction.
* The 6502 uses only one addressing mode per instruction, while the Z80 can combine two different addressing modes within a single instruction.
* The 6502 post-decrements on PHA and pre-increments on PLA, while the Z80 pre-decrements on PUSH and post-increments on POP.
* The 6502 saves flags automatically during interrupts; while the Z80 requires PUSH AF and POP AF.
* The 6502 only updates flags that are directly relevant to the operation's result. For example, EOR doesn't conceptually involve a carry, so the Carry flag is left untouched. On the Z80, XOR always clears the Carry flag to ensure a clean flag state.
<br>
* The ROR instruction didn't exist in the very earliest (pre-1977) chips. See: [https://www.pagetable.com/?p=406 Measuring the ROR Bug in the Early MOS 6502]
* The 6502 core used inside the [[NES]] is missing the Decimal Mode feature. [https://archive.org/details/nes-programmers-reference-guide-by-electronic-arts-1989/ NES programmer's reference guide] [https://www.nesdev.org/NESDoc.pdf NESDoc] [https://www.nesdev.org/wiki/Mapper NES mappers] [https://problemkaputt.de/everynes.htm Noca$h's Everynes] [https://www.nesdev.org/wiki/Emulator_tests NES emulator tests] [https://tcrf.net/Category:Nintendo_Console_Testing_Software Official Nintendo testing software]
* The 6507 CPU, used in the [[Atari VCS]], has only 13 address lines. So it can only address 8KB instead of 64KB. It also lacks the IRQ and NMI interrupt lines. [https://youtu.be/qvpwf50a48E Atari VCS: The Ultimate Talk] [https://cdn.hackaday.io/files/1646277043401568/stella.pdf Stella programmer's guide] [https://www.atarimania.com/documents/stella_system_training_manual.pdf Stella system training manual] [https://problemkaputt.de/2k6specs.htm Noca$h's 2k6specs]
* The HuC6280, used in the [[PC-Engine]] gaming console, is an improved version of the CMOS 65C02. [[Media:HuC6280 - CMOS 8-bit Microprocessor Hardware Manual.pdf|HuC6280 hardware manual]] [[Media:HuC6260 - CMOS Video Color Encoder Manual.pdf|HuC6260 VCE manual]] [[Media:HuC6270 - CMOS Video Display Controller Manual.pdf|HuC6270 VDC manual]]
* The WDC 65C816, used in the [[SNES]] and the [[Apple IIGS]], is a 16-bit version of the 65C02 [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet] [https://archive.org/details/SNESDevManual/ SNES development manual] [https://problemkaputt.de/fullsnes.htm Noca$h's fullsnes] [https://fabiensanglardsnes.netnesdev.org/wiki/ Fabien Sanglard's 2024 articlesSNESdev_Wiki SNESdev wiki]. The 65C816 contains a compatibillity mode, enabled by default upon reset, that makes it behave like a regular 65C02.
* The Sony SPC700 sound CPU used inside the SNES also behaves similarly to a 6502 with some extensions. [https://wiki.superfamicom.org/spc700-reference Source] [https://www.youtube.com/watch?v=zrn0QavLMyo&list=PLHQ0utQyFw5JD2wWda50J8XuzQ2cFr8RX SPC700 Series] [https://github.com/gilyon/snes-tests SNES-tests]
<br>
*[https://www.chibiakumas.com/6502/ Learn Assembly Programming with ChibiAkumas] Multi-platform 6502 tutorial
*[https://www.nesdev.org/obelisk-6502-guide/ Obelisk 6502 Guide]
*[https://www.masswerk.at/6502/6502_instruction_set.html 6502 Instruction Set] [https://www.masswerk.at/nowgobang/2021/6502-illegal-opcodes 6502 illegal opcodes demystified]*[[Media:NoMoreSecrets-NMOS6510UnintendedOpcodes-20212412.pdf|No more secrets - NMOS 6510 Unintended Opcodes]]
*[https://www.pagetable.com/c64ref/6502/?tab=2 6502 Family CPU Reference]
*[https://llx.com/Neil/a2/opcodes.html The 6502/65C02/65C816 Instruction Set Decoded]
*[https://www.nesdev.org/wiki/CPU_unofficial_opcodes Opcode matrix arrangement]
*[https://www.oxyron.de/html/opcodes.html Oxyron Opcode Matrices]
*[http://retro.hansotten.nl/uploads/books/Programming_the_6502.pdf Rodnay Zaks Programming the 6502]
*[http://www.6502.org/documents/datasheets/synertek/synertek_programming_manual.pdf Synertek SY650x programming manual (250 pages)]
*[http://www.6502.org/documents/datasheets/synertek/synertek_hardware_manual.pdf Synertek SY650x hardware manual (178 pages)]
*[[Media:SY6500 - SY65C02 datasheet.pdf]] - provides features a detailed breakdown of the machine cycles65C02 instructions*[https://xotmatrix.github.io/6502/ xotmatrix] 6502 instruction set and detailed cycle-by-cycle breakdown
*[[Media:6502 (65xx) Microprocessor Instant Reference Card.pdf]]
*[https://www.nesdev.org/wiki/CPU_interrupts 6502 Interrupts]
*[[Media:6502-dead-cycles.pdf]]
*[https://codebase64.org/doku.php?id=base:6510_instruction_timing 6510 Instruction Timing]
*[[Media:NoMoreSecrets-NMOS6510UnintendedOpcodes-20212412.pdf|No more secrets - NMOS 6510 Unintended Opcodes]]
*[https://youtu.be/fWqBmmPQP40 Conference - Reverse Engineering the MOS 6502 CPU]
*[https://floooh.github.io/visual6502remix/ Visual6502remix] [https://www.nesdev.org/wiki/Visual6502wiki Visual6502wiki]