#At the end of every instruction, the IRQ (if the interrupt disable flag is clear) and NMI pins are checked.
As an example, let M[$42]=$80, M[$43]=$10 and Y=$F1. The Then the instruction LDA ($42),Y will execute as follow, with phi2 ϕ2 as the first half-cycle and phi1 ϕ1 as the second half-cycle:
*T0: Fetch opcode $B1 (LDA (zp),Y) from memory then increment PC
*T1: Fetch operand byte $42 (zero page pointer address) then increment PC
*T2: Get low byte from zero page ($80)then increment the zero page address
*T3: Get high byte from next zero page location ($10) then add the Y register value ($F1) to $1080
*T4: Handle Garbage fetch from memory address $1071 then handle page boundary crossing (since $1080 + $F1 crosses a page)*T5: Read the value from memory address $1171 into the accumulatorthen no operation in the last half-cycle
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* The ROR instruction didn't exist in the very earliest (pre-1977) chips. See: [https://www.pagetable.com/?p=406 Measuring the ROR Bug in the Early MOS 6502]
* The 6502 core used inside the [[NES]] is missing the Decimal Mode feature. [https://archive.org/details/nes-programmers-reference-guide-by-electronic-arts-1989/ NES programmer's reference guide] [https://www.nesdev.org/NESDoc.pdf NESDoc] [https://www.nesdev.org/wiki/Mapper NES mappers] [https://problemkaputt.de/everynes.htm Noca$h's Everynes] [https://www.nesdev.org/wiki/Emulator_tests NES emulator tests] [https://tcrf.net/Category:Nintendo_Console_Testing_Software Official Nintendo testing software]
* The 6507 CPU, used in the [[Atari VCS]], has only 13 address lines. So it can only address 8KB instead of 64KB. It also lacks the IRQ and NMI interrupt lines. [https://youtu.be/qvpwf50a48E Atari VCS: The Ultimate Talk] [https://cdn.hackaday.io/files/1646277043401568/stella.pdf Stella programmer's guide] [https://www.atarimania.com/documents/stella_system_training_manual.pdf Stella system training manual] [https://problemkaputt.de/2k6specs.htm Noca$h's 2k6specs]