== I/O Access ==
The PSG has 16 read/writeable data registers, and a write-only index register. Only While there are only 16 data registers, the index register is 8-bit, not 4-bit. The higher 4 least significant -bits of the selected index register number are consideredused as chip select.
Both the index and data registers are accessed through [[8255|PPI Port A]], depending on the current setting of the BC1 and BDIR bits in [[8255|PPI Port C]]. The four possible combinations are:
=== 0Dh - Volume Envelope Shape (4bit) ===
Writing to this register (re-)starts the envelope. Both components of the envelope's phase are reset. The first step of the envelope has full duration every time. It is never shorted. [https://forums.nesdev.org/viewtopic.php?p=236672#p236672 Source]
The written value specifies the envelope shape, the four bits have the following meaning:
The possible combinations and resulting shapes are:
Here is the information transformed into a wiki table format:
{| class="wikitable"
| 1010 || 0Ah || <code>\/\/\/\/\/</code> ||
|-
| 1011 || 0Bh || <code>\"""""""""¯¯¯¯¯¯¯¯¯</code> || volume remains high
|-
| 1100 || 0Ch || <code>//////////</code> ||
|-
| 1101 || 0Dh || <code>/"""""""""¯¯¯¯¯¯¯¯¯</code> || volume remains high
|-
| 1110 || 0Eh || <code>/\/\/\/\/\</code> ||
|}
We can observe that there are only 8 resulting shapes even though they are selected by using a 4-bit value. The continue bit does not exist internally.==== Bit 3 (Continue) ====
In other wordsWhen bit3 = 0, in Python we havevolume and direction at the end of a period always are: def adsr_to_shape(val):volume = 0 if (val >> 2) = direction = 0: return 1 elif (val >> ==== Bit 2(Attack) == 1== This bit is only responsible for the starting point of the envelope and the direction. In other words, we have: return 7 return val & 7 volume = 0 if attack else 15 # Start at 0 for attack, 15 for decay direction = 1 if attack else -1 # Upward for attack, downward for decay
When using the volume envelope generator, the volume is always increased from 00h to 0Fh (or vice versa), it is not possible to specify a starting/ending point (like from 00h to 07h).
Writing to this register ==== Bit 1 (re-Alternate)starts and Bit 0 (Hold) ==== When bit3 = 1, these 2 bits determine what happens to volume and direction at the envelopeend of a period. volume = ~volume & 0x0F if !(alternate ^ hold) direction = 0 if hold else ~direction & 1 if alternate
=== 0Eh - External Dataregister Port A ===
== Noise Generator ==
The noise generator uses a [https://en.wikipedia.org/wiki/Linear-feedback_shift_register Linear-Feedback Shift Register] algorithm. It is described in detail in the [[Media:Microchip ay8930.pdf|AY-8930 datasheet]].
The noise generator uses a [https://en.wikipedia.org/wiki/Linear-feedback_shift_register Linear-Feedback Shift Register] algorithm. The random number generator of the 8910 is a 17-bit shift register. According to [https://github.com/mamedev/mame/blob/master/src/devices/sound/ay8910.h MAME]: The input to the shift register is bit0 XOR bit3. Bit0 is the output. This was verified on AY-3-8910 and YM2149 chips. However, the algorithm is described in detail in the [[Media:Microchip ay8930.pdf|AY-8930 datasheet]]. And it disagrees with MAME, the input to the shift register is bit0 XOR bit2. [[File:AY38910A noise block diagram.png]]
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The SSG has also been integrated as a component inside some of the arcade soundchips of the Yamaha OPN family. That's why you can find it in the [[Neo-Geo]] as a component inside the YM2610 soundchip. And the same is true for the OPN3 soundchip of the [[Play2CPC]] expansion.
The chip is clocked differently depending on the computer: ZX Spectrum: 1773400 Hz ; Pentagon: 1750000 Hz ; MSX: 1789772 Hz ; CPC: 1000000 Hz ; Oric: 1000000 Hz ; Atari ST: 2000000 Hz.
The PSG chip competed with the DCSG (Digital Complex Sound Generator) chip family (SN76489, SN94624, TMS9919) by Texas Instruments. The DCSG has similar sounding features except that it does not have any envelope control and that its noise generator has its own dedicated channel.