#At the end of every instruction, the IRQ (if the interrupt disable flag is clear) and NMI pins are checked.
As an example, let M[$42]=$80, M[$43]=$10 and Y=$F1. The Then the instruction LDA ($42),Y will execute as follow, with phi2 ϕ2 as the first half-cycle and phi1 ϕ1 as the second half-cycle:
*T0: Fetch opcode $B1 (LDA (zp),Y) from memory then increment PC
*T1: Fetch operand byte $42 (zero page pointer address) then increment PC
*T2: Get low byte from zero page ($80)then increment the zero page address
*T3: Get high byte from next zero page location ($10) then add the Y register value ($F1) to $1080
*T4: Handle Garbage fetch from memory address $1071 then handle page boundary crossing (since $1080 + $F1 crosses a page)*T5: Read the value from memory address $1171 into the accumulatorthen no operation in the last half-cycle
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