Changes
/* Bus arbitration */
Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how these signals are transformed into the Video Memory Address (VMA) .
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access
* The video hardware is given priority so that the display is not disrupted .
The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.
