On NMOS, DF is unchanged when entering an interrupt of any kind. This can cause unexpected bugs in the interrupt handler if Decimal Mode is on when an interrupt occurs. On CMOS, DF is automatically cleared on interrupt. Upon returning from an interrupt, the processor restores the status register from the stack, including DF.
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== IRQ / NMI / BRK / RESET ==
On a RESET, the CPU loads the vector from $FFFC/$FFFD into the program counter and continues fetching instructions from there.
On an NMI, the CPU pushes the low byte and the high byte of the program counter as well as the processor status onto the stack, disables interrupts and loads the vector from $FFFA/$FFFB into the program counter and continues fetching instructions from there.
On an IRQ, the CPU does the same as in the NMI case, but uses the vector at $FFFE/$FFFF.
On a BRK instruction, the CPU does the same as in the IRQ case, but sets bit #4 (B flag) in the copy of the status register that is saved on the stack.
The priority sequence for interrupts, from top priority to bottom, is as follows: RESET, BRK, NMI, IRQ. [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf Source at chapter 7.19]
On NMOS, NMI or IRQ that happens during specific moments of BRK execution can cause BRK to be effectively skipped. On CMOS, this situation is correctly handled by executing BRK and then servicing the interrupt.
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== IRQ / NMI / BRK / RESET Adressing Modes ==
On a RESET, the CPU loads the vector from {| class="wikitable"! Addressing Mode !! Example !! Operation|-| Immediate || LDA #$FFFC/EA || A ← $FFFD into the program counter and continues fetching instructions from there.EA|-On an NMI| Absolute || LDA $0314 || A ← M($0314)|-| Absolute, the CPU pushes the low byte and the high byte of the program counter as well as the processor status onto the stack, disables interrupts and loads the vector from X || LDA $FFFA/0314,X || A ← M($FFFB into the program counter and continues fetching instructions from there.0314+X)|-On an IRQ| Absolute, the CPU does the same as in the NMI caseY || LDA $0314, but uses the vector at Y || A ← M($FFFE/0314+Y)|-| Zeropage || LDA $FFFF.02 || A ← M($02)|-On a BRK instruction| Zeropage, the CPU does the same as in the IRQ caseX || LDA $02, but sets bit #4 X || A ← M(B flag$02+X) in the copy of the status register that is saved on the stack.|-The priority sequence for interrupts| Zeropage, from top priority to bottomY || LDA $02, is as follows: RESETY || A ← M($02+Y)|-| (Zeropage, BRK, NMIX) || LDA ($02, IRQ. [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf Source at chapter 7.19]X) || A ← M(PTR($02+X))|-On NMOS| (Zeropage), NMI or IRQ that happens during specific moments of BRK execution can cause BRK to be effectively skipped. On CMOSY || LDA ($02), this situation is correctly handled by executing BRK and then servicing the interrupt.Y || A ← M(PTR($02)+Y)|}
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* NOP abs,X (opcodes DC, FC) are broken versions of CPY abs,X and CPX abs,X
* NOP # (opcodes 80, 82, 89, C2, E2) are the useless instructions STY #, STX #, STA #, DEC #, INC #
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== Adressing Modes ==
{| class="wikitable"
! Addressing Mode !! Example !! Operation
|-
| Immediate || LDA #$EA || A ← $EA
|-
| Absolute || LDA $0314 || A ← M($0314)
|-
| Absolute,X || LDA $0314,X || A ← M($0314+X)
|-
| Absolute,Y || LDA $0314,Y || A ← M($0314+Y)
|-
| Zeropage || LDA $02 || A ← M($02)
|-
| Zeropage,X || LDA $02,X || A ← M($02+X)
|-
| Zeropage,Y || LDA $02,Y || A ← M($02+Y)
|-
| (Zeropage,X) || LDA ($02,X) || A ← M(PTR($02+X))
|-
| (Zeropage),Y || LDA ($02),Y || A ← M(PTR($02)+Y)
|}
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