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6502

80 bytes added, 5 September
/* Half Cycles */
* On NMOS, when adding a carry to the MSB of an address, a fetch occurs at a garbage address. On CMOS, the last byte of the instruction is refetched.
* On NMOS, when doing a fetch-modify-store instruction (INC, DEC, ASL, LSR, ROL, ROR), garbage is stored into the location during the "modify" cycle... followed by the "real" store cycle which stores the correct data. On CMOS, a second fetch is performed instead of a garbage store.
 
The 6510 CPU adds an AEC pin that the VIC-II uses to kick the CPU off the bus.
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