Changes
CRTC
,/* Signal delay */
But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal.
So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious source of incompatibilityissue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4.
==== Discolouration effect ====
