Changes
/* Bus arbitration */
== Bus arbitration ==
The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).
Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs
* The Gate-Array fetches two bytes for each address
* The video hardware is given priority so that the display is not disrupted
The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing while the video-hardware is accessing it.
As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.
== Interrupt generation ==
