Changes
CRTC
,/* HSYNC */
=== HSYNC ===
The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed no HSYNC is generated(and therefore, no interrupts). On CRTCs 2/3/4, if 0 is programmed this gives an HSYNC width of 16.
==== Signal delay ====
