Changes
ASIC
,/* DMA sound channels */
All instructions execute in 1 cycle, except LOAD which requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the PPI, or 2 extra cycles if the CPU access was itself a PSG register write.
A pause prescaler register (PPR) is available for each channel to define the pause unit. It is expressed in number of HSYNCs.
The DMA control and status register DCSR (at address 6C0Fh) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
