All of these are almost identical in their operation. It is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back.
<br>
== The 8255 in the CPC ==
In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the [https://cpctech.cpcwiki.de/docs/cpcplus.html Extra CPC+ documentation] for more information.
<br>
== Port Usage ==
* NOTE - If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not.
<br>
== PPI Port A ==
|-
|}
<br>
== PPI Port B ==
* If port B is programmed as an output, you can make a fake vsync visible to the Gate-Array by writing 1 to bit 0. You can then turn it off by writing 0 to bit 0. It is fake in the sense that it is not generated by the CRTC as it normally is. This fake vsync doesn't work on all CPCs. It is not known if it is dependent on CRTC or 8255 or both.
* For more info on LK1-LK4 (and further LKs) see [[LK Links]]
<br>
== PPI Port C ==
|-
|}
<br>
== PPI Control ==
This register has two different functions depending on bit7 of the data written to this register.
<br>
=== PPI Control with Bit7=0 ===
Bit 7 SF Must be "0" in this case
[[File:Intel 8255A - BSR control word format8255 Control0.jpgpng]] <br>
=== PPI Control with Bit7=1 ===
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.
[[File:Intel 8255A - IO modes control word format8255 Control1.jpgpng]] <br>
== Group Modes ==
In some of these modes, port C is used as a control/status port for port A or B. It can be used to confirm when data transfer may take place, and reflect any other flags. The 8255 PPI is therefore supplied with the added option for the user to set or reset any individual bits in port C.
<br>
=== Mode 0 – Simple Input/output mode ===
[[File:8255 - mode-0.png]]
<br>
=== Mode 1 – Strobed Input/output or Handshake mode ===
[[File:8255 - mode-1.png]]
<br>
=== Mode 2 – Bidirectional Mode ===
[[File:8255 - mode-2.png]]
<br>
=== Port pins summary ===
[[File:8255 - Port pins.gif]]
<br>
== Programming Examples ==
</pre>
= Diagram =<br>
[[File:== Block-diagram-of-8255-l.jpg]]Diagram ==
[[File:8255 Block Diagram.png]] <br> == Amstrad ASIC PPI == *The 8255 PPI is not emulated by the Pre-ASIC. These CPCs have a real PPI chip and therefore behave like the first generation of CPCs.*The ASIC PPI does not support Group Modes other than Groupe Mode 0.*On the ASIC PPI, Port B is always defined as input and Port C is always defined as output.*On a real PPI chip, when the PPI control register is used (with bit7=1) to configure the ports, the output latches of all ports are reset to 0. The ASIC poorly emulates the PPI and does not reset these ports. <br> == Resources ==
* [[Media:Intel8255A_datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PIO]]PPI
<br> == Links ==
*[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]
*[http://quasar.cpcscene.net/doku.php?id=assem:ppi Quasar PPI documentation (in french)]
[[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]