The Programmable Sound Generator (PSG) of the CPC is an AY-3-8912 chip. It is able to output three separate sound channels (named Channel A, B and C). Each channel can be used to output tones and/or white noise.
== PSG Registers ==
===05h - Channel C Tone Frequency High (4bit)===
The tone (square wave) frequency in Hertz is calculated as follows:
F = 4MHz 1MHz / 64 16 / nn ;with nn in range 1..4095 (nn=0 acts as nn=1)
Possible frequencies are in range from 62500Hz (nn=1) down to approx. 15.26Hz (nn=4095).
The noise frequency in Hertz is calculated as follows:
F = 4MHz 1MHz / 64 16 / nn ;with nn in range 1..31 (nn=0 acts as nn=1)
Noise can be output on all 3 channels, but there is only one noise generator (so all channels share the same noise frequency). The noise generator consists of 17bit shift register, and a 1bit noise level (0=LOW or 1=HIGH). These are updated at the selected frequency as follows:
Envelope step frequency (tone or noise) calculated as follows:
F = 4MHz 1MHz / 64 16 / nn ;with nn in range 1..65535 (nn=0 acts as nn=1)
Depending on the envelope shape, the volume is incremented from 0 to 15, or decremented from 15 to 0. In either case it takes 16 steps to complete, the completion time for 16 steps is therefore:
T = nn*1024 256 / 4MHz 1MHz ;with nn in range 1..65535 (256us .. 16.7 seconds)
=== 0Dh - Volume Envelope Shape (4bit) ===
Otherwise (when using the built-in speaker), all three channels are mixed at the same intensity. This signal appears to be also sent to the Tape output line also, so a connected Data Recorder could be used to record CPC music also.
== Noise Generator ==
The noise generator uses a [https://en.wikipedia.org/wiki/Linear-feedback_shift_register Linear-Feedback Shift Register] algorithm.
According to the [https://github.com/mamedev/mame/blob/master/src/devices/sound/ay8910.h MAME developers], the Random Number Generator of the 8910 is a 17-bit shift register. The input to the shift register is bit0 XOR bit3. Bit0 is the output. This was verified on AY-3-8910 and YM2149 chips.
== D/A converter table ==
0, 231, 695, 1158, 2084, 2779, 4168, 6716, 8105, 13200, 18294, 24315, 32189, 40757, 52799, 65535
For the record, these are [https://groups.google.com/g/comp.sys.sinclair/c/-zCR2kxMryY Matthew (Gasman) Westcott measurements] (normalised) on its ZX Spectrum:
0, 0.0105, 0.0154, 0.0216, 0.0314, 0.0461, 0.0635, 0.1061, 0.1319, 0.2163, 0.2973, 0.3908, 0.5129, 0.6371, 0.8186, 1
ay3 manual show different values:
== Block Diagram ==
*[[File:PSG Block Diagram.png]]
== Schematics ==
The PSG is driven by an external clock at 1MHz provided by the [[Gate Array]].
The AY chip has an internal clock divider by 8 which means that it works internally at 125KHz, outputting 125,000 samples per second for each channel.
The BC2 and A8 pins are always equal to 1 as they are connected to +5V.
The /A9 pin is non-existent on the AY-3-8912 model.
== Datasheet ==