Changes

Upgrade of [[Category:DIY]] [[Category:Memory expansions]]A project to upgrade a CPC6128 to 512K RAM (total), done by replacing the CPC 6128CPC6128's internal RAM to 512 KiB as proposed in chips, and its PAL banking chip, the article '''Aus David wird Goliath: 512 KB RAM für Schneider CPC''' project was released 1987 in issue 10/1987, pages 156 to 162 of the German IT german magazine '''c'tMagazin'''. The DIY project name is '''CPC 6512'''. The mod requires to remove (or disable) the sixteen RAM chips on the CPC6128 mainboard, and to replace them by bigger chips, plus whatever additional bank selection logic.

The memory is accessed via Port 7Fxxh, as on [[Standard Memory Expansions]]* '''PAL Replacement''' - Replace the old PAL (IC118) by the new daughterboard. Since Most signals connect to the internal RAM is removed, its total capacity is only 512K PAL socket (unlike standard 512K expansions which provide 64K internal plus 512K external memorygreen in schematic), ie. 576K totala extra few wires connect elsewhere on mainboard (red). Altogether, as an optional "bonus" feature, the c't expansion works like circuit contains logic for a 448K dk'tronics expansion 3rd floppy drive (leaving the banks selected via OUT [7Fxxh],FCh..FFh unusedblue).

One half (256K) of the total (512K) expansion memory can be accessed as Video RAM (with normal expansions, only 64 KB are accessible as VRAM)<gallery>File:CPC6512 ct magazin schematic. This is making the expansion slightly incompatible with the dk'tronics standardpng|SchematicFile:CPC6512 ct magazin pcb. However, usually expansion memory is mapped to 4000h-7FFFh, whilst VRAM is usually mapped to C000h-FFFFh. So, most existing software may work with it, without accidently displaying garbage on the screen. == Installation Guide ==jpg|PCB=== Components ===</gallery>

1x PAL 16L8 ;replacing the CPC6128's 16 built-in PAL 1x 74LS38 ( ;Quad 2-input NAND, OC) 1x 74LS273 ( ;8bit latch, of which only 6bit 5bit are used here) 1x 2200 Ohm resistor ;pull-up for OC output 1x 470 Ohm resistor ;pull-up for OC output 1x 47 Ohm resistor ;purpose unknown (noise related? shortcut protection?)

=== Step 1 - Replacing the RAM =Compatibility Problems ==

* RAMDIS is not supported, not a problem in most cases, but won't work with some special types of expansion hardware, like [[Multiface II]].* The old 64Kx1 DRAMs expansion seems to have same pin-outs as been designed independently of [[Standard Memory Expansions]] like the new 256Kx1 ones dk'tronics one. So, there is no (exceptintended) compatibility. However, pin 1 was NC on old chips, on new chips itboth c's A8 of RASt and dk'tronics are designed around the CPC6128 banking mechanism, so they do work similar in some ways. Namely, both can map expansion banks to 4000h..7FFFh, but there are several differences:CAS addresses; aka A16** For the mapping to 4000h..7FFFh,A17 dk'tronics uses values CCh..CFh, D4h..C7h, DCh..DFh, ... FCh..FFh whilst c't uses values C8h..DFh. Some of linear addressesthese values do overlap, resulting in some (unintended)semi-compatibility, but there's still one big difference: along with the above values, dk'tronics maps bank 3 to C000h..FFFFh, whilst c't maps bank 7 to that region.

=== Step 2 The memory is controlled by OUT [7Fxxh],C0h..DFh instructions. Values C0h..C7h are working same as on normal CPC6128s. Values C8h..DFh do access the additional RAM banks (C8h..D3h when using the cut- Daughterboard Logic ===down 320K upgrade variant).

The original article has been confusing on this part. It basically said that one needs "four additional connections" OUT [7Fxxh], but without giving too clear info on which signals are to be connected to which locationsC0h+... 0 1 2 3 4 5 6 7 8..31 ------------------------------------------------------- Bank at C000h..FFFFh 3 7 7 7 3 3 3 3 7 (!) Bank at 8000h..BFFFh 2 2 6 2 2 2 2 2 2 Bank at 4000h..7FFFh 1 1 5 3 4 5 6 7 8..31 Bank at 0000h..3FFFh 0 0 4 0 0 0 0 0 0

* Replace the old == PAL by the new daughterboard (containing the new PAL, and the 2 logic chips and 3 resistors).Source Code ==

D7D6 D0 D3 D4 D1 D2 NCAS A15 A14 GND ;pin 1..10 CPU A15S AMUX MUX LCLK CAS1 CAS0 IOWR A14S VCC ;pin 11..20 IF (VCC) /LCLK= D7D6 * RAMDIS is not supported/A15 * /IOWR ;load external latch on OUT [7Fxxh], not a problem in most casesC0h..FFh IF (VCC) /CAS0= /NCAS * /D4 + ;bank bit4=0, but won't work with some special types of expansion hardwareselect bank 0..15 (CPU and CRTC) /CAS0= /NCAS * A15 + /CAS0= /NCAS * /A14 + /CAS0= /NCAS * CPU IF (VCC) /CAS1= /NCAS * D4 * /A15 * A14 * /CPU ;bank bit4=1, like [[Multiface II]]select bank 16..31 (CPU at 4000h..7FFFh only) IF (VCC) /A14S= /A14 + ;bank bit0 /D0 * D2 * /A15 + /D0 * D3 * /A15 + /D0 * D4 * /A15 IF (VCC) /A15S= /A14 * /A15 + ;bank bit1 /D1 * /A15 + /D4 * /D3 * /D2 * /D0 * /A15 + /D4 * /D3 * /D2 * /D1 * /A15 IF (VCC) /AMUX= /D0 * D1 * /D2 * /D3 * /D4 * /CPU * /MUX + A15 * A14 * /D2 * D0 * /CPU * /MUX + A15 * A14 * /D2 * D1 * /CPU * /MUX + A15 * A14 * D3 * /CPU * /MUX + A15 * A14 * D4 * /CPU * /MUX + /A15 * A14 * D2 * /CPU * /MUX + ;bank bit2 /A15 * A14 * D3 * /CPU * MUX ;bank bit3 IF (GND) /MUX = /MUX ;dummy (do not output anything on this pin) IF (GND) /IOWR=/IOWR ;dummy (do not output anything on this pin)

* Unknown which banks are usable as VRAMSome notes on the syntax:** The first four 16K bank two lines assign the pin-outs. Observe that leading "/" slashes are omitted here. For example, "/CPU" (probablyin schematic) usuable as VRAM becomes "CPU" (as on all 64K CPC modelsin source code). Accordingly "/CPU" (in source code) would be double-negated "//CPU" aka "CPU" (in schematic).** The next four 16K bank are "IF (hopefullycondition) not usuable as VRAM signal=" part means that "signal" becomes an output when condition is true. In the above source code, condition is always true (VCC), or, for CP/M+ compatibilitythe last 2 lines, which uses them as Work RAMalways false (GND).*The "* For further banks it's totally unknown if they " and "+" operators are used as VRAM or notmeaning "* Unknown if it's fully dk'tronics compatible= AND", or more like incompletely implemented Inicron variant* Unknown what happens on accessing the unused region via OUT [7Fxxh],FCh."+ = OR".FFhThe idea behind that confusing syntax was to make it "easier" to learn for people who are trained only in basic maths (the formulas do also work when treating * Chipset / Schematic is unknown =multiply, and += Newer Info plus. For example: 1+0+1+1 =3 =nonzero = true). Having a short look at the article, it seems to * There must be all different as than expectedsome priority ordering in the formulas: Either * There is no dk'tronics compatibility intended - howeverbefore +, c't and dk'tronics are based on or operations inside of a line before merging the CPC6128 banking mechanism, so they work similar, and to some level there is some (unintended) compatibility. Namely, ONE HALF results of the memory can be accessed separate lines (in dk'tronics style fashion. * There seems to be no hardware based "Video RAM" support at all. Howeverabove examples, there's some unspectacular software based example included that copies expansion RAM to VRAM via LDIR opcodeboth ordering methods do work).

* [[Media:CPC6512 ct magazin part 1.pdf]] - c't issue 10/1987 - RAM Expansion Schematic* [[Media:CPC6512 ct magazin part 2.pdf]] - c't issue 11/1987 - RAM Disc driverfor CP/M Plus

== Related hardware modifications ==* [[CPC_6320_/_CPC_6512_-_internal_320K_/_512K_for_CPC_6128|CPC 6320 / CPC 6512 (by eto) - similar logic, but fully standards compatible]]* [httphttps://cpcwiki.eu/forum/index.php/topic,662.msg7113.html#msg7113 Bank Swapper by Khany/Cherry-T] (less complex: bank-exchanging toggle, no memory expansion; 1993)