Changes

Gate Array

168 bytes added, Saturday at 19:44
/* CSYNC signal */
For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 included.
The same logic applies to On Gate Array, even if the duration of the CRTC VSYNCis reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines instead of chars. The Gate Array C-VSYNC is considered complete when to the 26th line has been processedmonitor. Then While on ASIC/Pre-ASIC, the Gate Array stops outputting CRTC VSYNC must be active for the palette colour blackC-VSYNC signal to be sent by the ASIC to the monitor.
The Gate Array uses 2 internal counters to create its CSYNC signal:
* H06 which counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.* V26 which counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2. It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.
The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
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== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]
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*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
 
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== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]
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