*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
Note: On Amstrad Plus, the Gate Array is not the sole generator of interrupts. The 3 DMA sound channels are each able to trigger an interrupt. Also, the ASIC offers a programmable raster interrupt register (PRI) that can be used instead of the normal raster interrupt mechanism.
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The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".
The recommended I/O port address is &7Fxx.
The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 the first bits of the data define the function selected (see table below). It is not possible to read from the Gate-Array.
{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
!colspan=4|''Data Bit 7''8bit command!rowspan=2|Machine!rowspan=2|''Data Bit 6''Register!rowspan=2|Description!rowspan=2|''Function''Chip
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| ! 7! 6! 5! 4..0 || 0 || Select pen
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| 0 || 1 0 || x || style="text-align: center;" | n || All || PENR || Select colour for selected pena color register || Gate Array
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| 0 || 1 || 0 x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Select screen mode, ROM configuration and interrupt controlGate Array
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| 1 || 1 0 || RAM Memory Management (note 1)0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
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| 1 || 0 || 1 || style="text-align: center;" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
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| 1 || 0 || 1 || style="text-align: center;" | n || Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
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| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL
|}
===== Note =====The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.
This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function MMR is performed in a an external memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function MMR is not available. In the CPC6128, this function MMR is performed by a [[PAL16L8|PAL]] located on the main PCB, or a an external memory-expansion. In the 464+ and 6128+ this function , MMR is performed by the ASIC or a an external memory expansion. Please read the document on RAM management for more information.
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== Registers == Note: The Plus palette capabilities are only accessible through the ASIC I/O page. Registers PENR and INKR are not needed in that case. === Register 0 - Palette Index PENR (Pen selectionSelect a color register) ===
When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.
Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}
| ''Bit'' || ''Value'' || ''Function''
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| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"PENR register
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| 6 || 0
| ''Bit'' || ''Value'' || ''Function''
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| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"PENR register
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| 6 || 0
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=== Register 1 - Palette Data INKR (Colour selectionChange the value of the currently selected color register) ===
Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.
Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}
| ''Bit'' || ''Value'' || ''Function''
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| 7 || 0 || rowspan="2" | Gate Array function "Colour selection"INKR register
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| 6 || 1
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=== Register 2 - Select screen mode and RMR (Control Interrupt counter, ROM configuration mapping and Graphics mode) ===
This is a general purpose register responsible for the [[Video modes|screen mode]] and the ROM configuration.
=== Screen = Graphics mode selection ====
The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.
==== ROM configuration selection ====
Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.
Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}
| ''Bit'' || ''Value'' || ''Function''
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| 7 || 1 || rowspan="2" | Gate Array functionRMR register
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| 6 || 0
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| 5 || - || not used''must be 0 on Plus machines with ASIC unlocked''
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| 4 || x || Interrupt generation control
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
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| 1 || x || rowspan="2" | Screen Graphics Mode slectionselection
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| 0 || x
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=== Register RMR2 (ASIC & Advanced ROM mapping) === This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked. {|{{Prettytable|width: 700px; font-size: 2em;}}|-| ''Bit'' || ''Value'' || ''Function''|-| 7 || 1 || rowspan="3 " | Gate Array RMR2 register|- | 6 || 0|-| 5 || 1|-| 4 || x || rowspan="2" |Lower ROM address and ASIC I/O page mode|-| 3 || x|-| 2 || x || rowspan="3" | Physical lower ROM number (0..7)|-| 1 || x|-| 0 || x|} The lower ROM address and ASIC I/O page modes are: -Mode- ROM address ASIC I/O Page 00 &0000-&3FFF Disabled 01 &4000-&7FFF Disabled 10 &8000-&BFFF Disabled 11 &0000-&3FFF &4000-&7fff The physical lower ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register. <br> === Register MMR (RAM Banking memory mapping) ===
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.
| ''Bit'' || ''Value'' || ''Function''
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| 7 || 1 || rowspan="2" | Gate Array function 3MMR register
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| 6 || 1
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| 5 || b x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
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| 4 || bx
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| 3 || bx
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| 2 || x || rowspan="3" | RAM Config (0..7)