*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
== CSYNC signal ==
On CPC, the HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then converted modified and merged by the Gate Array into a single CSYNC signal that will be sent to the display. When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs. The HSYNC pulse width needs to be at least 2µs for Gate Array to change the video mode. The HSYNC is modified before being sent to the monitor. It happens 2µs after the HSYNC from the CRTC and stay a maximum of 4µs (signal is cut short if HSYNC width is greater than 6). For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 included. The VSYNC is also modified before being sent to the monitor. It happens 2 lines* after the VSYNC from the CRTC and stay a maximum of 2 lines (same cut rule if VSYNC is greater than 4). PAL (50Hz) does need two lines VSYNC_width, and 4µs HSYNC_width.
The Gate Array uses 2 internal counters to create its CSYNC signal:
* H06 which counts the number of CRTC characters processed during an HSYNC
* V26 which counts the number of HSYNCs occuring during a VSYNC
On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array.
== Controlling the Gate Array ==