NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
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== Overview ==
4. As far as I know, the KC compact used HD6845R only.
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== Timings and relating with Z80 instructions count ==
Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106
(To be extracted/edited to conform to wiki good practices).
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==Programming==
2. The CRTC is not connected to the CPU's RD and WR pins, so the CRTC is not aware of the CPU bus I/O direction. Therefore, if you perform an IN instruction to the select or write functions, it will write data to the CRTC from the current data on the bus.
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==Addressing==
The following table defines the generated video memory address VMA of the [[Gate Array]] is constructed from the CRTC MA and Gate-Array RA signals.
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Video Memory Address Signal''||''Signal source''||''Signal name''
|-
|A15||6845||MA13
|}
CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the its current graphics modeand palette.
CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.
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== CUDISP (aka CURSOR) ==
However, this signal is provided to the expansion port. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.
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== DISPTMG (aka Display Enable) ==
The DISPTMG can be forced to 0 by using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2.
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== HSYNC and VSYNC ==
The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed no HSYNC is generated. On CRTCs 2/3/4, if 0 is programmed this gives a HSYNC width of 16.
During an HSYNC, if HSYNC width is changed with a value less than the current HSC, then HSC is overflowing. The only exception is for CRTC 1 with a value of 0, which cancels the current HSYNC.
CRTCs 1/2 have a fixed VSYNC width value of 16. VSYNC width can be configured with Register 3 on CRTCs 0/3/4. If 0 is programmed this gives 16 lines of VSYNC.
The bit 0 of port B of the PPI changes to 1 as soon as the VSYNC signal is produced by the CRTC.
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== The 6845 Registers ==
So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.
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== CRTC Differences ==
* See the document "Extra CPC Plus Hardware Information" for more details.
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=== Horizontal and Vertical Sync (R3) ===
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
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=== Interlace and Skew (R8) ===
2 interlace modes are available:
* In interlace sync mode, the same information is painted in both fields to enhance readability. In this mode, reprogramming the CRTC is not necessary
* In interlace sync and video mode, alternating lines are displayed in the even and odd field to double the resolution. In this mode, it is necessary to reprogram the CRTC as if we were building a frame of 624 lines. The 625th line is managed automatically by the CRTC
[[File:CRTC Interlace modes.png]]
<br> === UM6845R and R31 on Type 1 ===
R31 is described in the UM6845R documentation as "Dummy Register".
R31 doesn't exist on types 0,2,3,4.
<br> === UM6845R and R12/R13 on Type 1 ===
The UM6845R differs to other CRTC in respect of R12/R13.
In demos to make a display compatible with all CRTCs, program R12/R13 when VCC!=0. This will then take effect at the next frame start.
<br> === UM6845R status Status register on Type 1 ===
The UM6845R has a status register that can be read using port &BExx.
All the other bits read as 0 and don't have any function.
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=== R10/R11 on ASIC/Pre-ASIC ===
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}
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=== Reading from CRTC registers on ASIC/Pre-ASIC ===
No matter its type, the CRTC never buffers its counters.
The only value that is saved in a buffer in the CRTC is the video pointer MA because it is reloaded at each line start. The exception is the CRTC 1 for which the MA is reloaded with R12/R13 instead of MA' as long as C4=0.
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* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1. In this document, the line numbers in the figure 7 for the "Interlace Sync and Video" mode is incorrect
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2 [[Media:Mc6845.pdf|Other datasheet version]]
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3
* [[AMS40226 (Amstrad)]] aka Type 4
*[[Media:CRTC-5-HD6345.pdf|HD6345 (Hitachi)]] aka Type 5 - Upgraded pin-compatible CRTC chip with advanced functionalities [https://thecheshirec.at/2024/05/07/un-crtc6345-sur-amstrad-cpc/ Upgrading the CPC to HD6345]
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== Unused clones ==
* [[CM607P]] a Bulgarian clone made in Pravetz factory
* [[Media:EF6845P.pdf|EF6845PEF6845]] by Thomson Semiconductors
* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC
* [[Media:F6845.pdf|F6845]] by Fairchild
* [[Media:Mos 6545-1 crtc.pdf|CRTC 6545]] (MOS, Rockwell, Synertek) is pin-compatible with the 6845 and only has minor differences
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845
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== Tools about CRTC ==
* [[File:Shaker26.dsk]] Shaker - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)
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== Links ==
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [[Media:ACCC1.8-EN.pdf]] [[Media:ACCC1.8-FR.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
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==Related pages==