CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.
== CUDISP (aka CURSOR) ==
CUDISP (Cursor Display) signal defines the hardware cursor.
CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.
However, this signal is provided to the expansion port. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.
== DISPTMG (aka Display Enable) ==
DISPTMG (Display Timing) signal defines the border. When DISPTMG is "10" the border colour is output by the Gate-Array to the display.
The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
The DISPTMG can be forced to 0 by using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2.
== HSYNC and VSYNC ==
The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed no HSYNC is generated. On CRTCs 2/3/4, if 0 is programmed this gives a HSYNC width of 16.
During an HSYNC, if HSYNC width is changed with a value less than the current HSC, then HSC is overflowing. The only exception is for CRTC 1 with a value of 0, which cancels the current HSYNC.
CRTCs 1/2 have a fixed VSYNC width value of 16. VSYNC width can be configured with Register 3 on CRTCs 0/3/4. If 0 is programmed this gives 16 lines of VSYNC.
|2||Horizontal Sync Position ||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (Needs to be at least 2 for Gate Array to change the video mode); VSync width in scan-lines (Not present on all CRTCs, fixed to 16 lines on these); HSync pulse width in characters.
|-
|4||Vertical Total (-1)||x0000000||38||Height of the screen, in characters.
Interlace 2 interlace modesare available:* In interlace sync mode, the same information is painted in both fields to enhance readability. In this mode, reprogramming the CRTC is not necessary* In interlace sync and video mode, alternating lines are displayed in the even and odd field to double the resolution
[[File:CRTC Interlace modes.png]]
! Abbr
! Alternate name
! Comment
|-
|Horizontal Character Counter
|HCC
|C0
|
|-
|Horizontal Sync Counter
|HSC
|C3l
|
|-
|Vertical Character Counter
|VCC
|C4
|
|-
|Vertical Sync Counter
|VLC
|C9
|If non-interlace, this counter is exposed on CRTC pins RA0..RA4
|-
|Vertical Total Adjust Counter
|VTAC
|C5 (or C9 |This counter does not exist on CRTCs 0/3/4). C9 is reused instead
|-
|Frame Counter
|FC
|''|Used for to alternate frames in interlace and for CRTC cursor blinking''|-|Memory Address|MA||This counter is exposed on CRTC pins MA0..MA13
|}
No matter its type, the CRTC never buffers its counters.
The only value that is saved in a buffer in the CRTC is the video pointer MA because it is reloaded at each line start.
<br>
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1. In this document, the figure 7 describing the "Interlace Sync and Video" mode is incorrect
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2 [[Media:Mc6845.pdf|Other datasheet version]]
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3
== Unused clones ==
* [[CM607P]] a Bulgarian clone made in Pravetz factory
* [[Media:EF6845P.pdf|EF6845P]] by Thomson Semiconductors* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC* [[SY6845EAMedia:F6845.pdf|F6845]] by SynertekFairchild* [[F68B45PMedia:Mos 6545-1 crtc.pdf|CRTC 6545]] by Freescale* CRTC6545 (MOS, Rockwell, Synertek) is pin-compatible with the 6845 and only has minor differences
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845