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==Amstrad Custom custom chips==
The Amstrad CPC used one custom chip: the video [[Gate Array]] (also called VGA – no connection with the Video PC standard).
This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".
*12-bit colour palette*Hardware Sprites.sprites*Soft Vertical and horizontal per-pixel hardware soft scrolling (in complement with register 12&13 of the CRTC)
*Screen splitting
*Programmable and vectorised raster interrupts*Vectored interrupts
*DMA sound channels
*Specific ROM switching
*8-bit printer port (with bit3 of CRTC register 12)
*Analog joystick port
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== Analog joystick == Analog joystick axes are unsigned 6-bit values. Bits7..6 are always 0. <br> == Colour palette == A colour in the palette is coded in 2 bytes:* For first byte, bits7..4 are blue value, bits3..0 are red value* For second byte, bits7..4 are ignored, bits3..0 are green value <br> == Hardware sprites == Sprites are prioritized so that the border has the highest priority, followed by sprites 0 to 15 in sequence, then the main screen data. There is only one pixel per byte in sprite image data. Bits3..0 of each byte define the palette index for this pixel. Bits7..4 are ignored. Each sprite magnification is coded in 1 byte:* bits7..3 are ignored* bits3..2 are X magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4)* bits1..0 are Y magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4) <br> == Soft Scroll scroll ==
The 8-bit register SSCR (at address 6804h) controls soft scrolling by pixels rather than by characters. Setting this register to 0 (the default value at power-up) disables the soft scroll feature. The soft scrolling mechanism affects the entire main screen, regardless of the split screen feature, but does not affect sprites.
* Bit3Bits3..0 of SSCR defines define a horizontal delay between 0 and 15 high-resolution (mode 2) pixels, shifting the screen image to the right by the programmed value. This causes pixels to be lost behind the right border and random data to appear on the left. Also the programmer must ensure that the delay value is a multiple of the number of bits per pixel.* Bit6Bits6..4 of SSCR is added are summed to the least significant 3 bits of the scan line address, determining which of the eight 2k blocks contains the data for the first scan line on the screen. This shifts the display up by the programmed number of scan lines, causing the first lines to be lost and extra lines to appear at the bottom.
* Bit7 of SSCR, when set, extends the border to cover the first 2 bytes (16 high-resolution pixels) of each scan line, masking bad data caused by the horizontal soft scroll. When using horizontal soft scroll, always set this bit to maintain consistent screen width.
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== Split Screen screen ==
The 8-bit register SPLT register (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value at power-up) disables the split screen feature.
The 16-bit register SSA register (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen. SSA works similarly to the duo R12/R13 in the CRTC. This configuration allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screenregardless.
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== Programmable Raster Interrupt raster interrupt ==
The 8-bit memory-mapped register PRI (at address 6800h) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power-up) reverts to the classic [[Gate Array]] R52 raster interrupt system instead.
A The DMA control and status register (DCSR(at address 6C0Fh) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
* Bits2..0 are the channel enable bits. When set to "1" it enables the corresponding DMA channel. It can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on rest.
* Bits7..4 are the interrupt bits. An interrupt bit is set to "0" when the corresponding channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
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== Vectored Interrupt interrupt ==
The ASIC always provides an interrupt vector on interrupt request.
The register IVR (at address 6805h) supplies the top 5 bits of the vector provided to the CPU. It IVR is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt mode, always set up the IVR so that the top 5 bits are defined.
Bits2..1 of the IVR register are unused.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
==== Interrupt Vector vector used on Z80 IM2 mode ====
{| class="wikitable"
|-
!Interrupt Vectorvector
!Signal source
!Value
|A7..A3||ASIC||IVR register bits7..3
|-
|A2..A1||ASIC||00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA rasterRaster
|-
|A0||ASIC||Always 0
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== Known Flawsflaws==
The Amstrad Plus ASIC improved a lot of the old CPC's capability.
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==Internal Linkslinks==
*[[Arnold V specs]]
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==External Linkslinks==
*[http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC at Wikipedia] General information on ASICs.