The ASIC provides an interrupt vector on interrupt request.
The register IVR (at address 6805h) supplies the top 5 bits of the vector provided to the CPU. It IVR is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt mode, always set up the IVR so that the top 5 bits are defined.
Bits2..1 of the IVR register are unused.