*Specific ROM switching
*8-bit printer port (with bit3 of CRTC register 12)
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== Soft Scroll ==
The 8-bit register SSCR (at address 6804h) controls soft scrolling by pixels rather than by characters. Setting this register to 0 (the default value at power-up) disables the soft scroll feature. The soft scrolling mechanism affects the entire main screen, regardless of the split screen feature, but does not affect sprites.
* Bit3..0 of SSCR defines a horizontal delay between 0 and 15 high-resolution (mode 2) pixels, shifting the screen image to the right by the programmed value. This causes pixels to be lost behind the right border and random data to appear on the left. Also the programmer must ensure that the delay value is a multiple of the number of bits per pixel.
* Bit6..4 of SSCR is added to the least significant 3 bits of the scan line address, determining which of the eight 2k blocks contains the data for the first scan line on the screen. This shifts the display up by the programmed number of scan lines, causing the first lines to be lost and extra lines to appear at the bottom.
* Bit7 of SSCR, when set, extends the border to cover the first 2 bytes (16 high-resolution pixels) of each scan line, masking bad data caused by the horizontal soft scroll. When using horizontal soft scroll, always set this bit to maintain consistent screen width.
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== Split Screen ==
The 8-bit register SPLT (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value at power-up) disables the split screen feature.
The 16-bit register SSA (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen. SSA works similarly to the duo R12/R13 in the CRTC. This configuration allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screen.
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== Programmable Raster Interrupt ==
The 8-bit memory-mapped register PRI (at address 6800h) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power-up) reverts to the classic [[Gate Array]] R52 raster interrupt system instead.
PRI can be reprogrammed as required to produce multiple interrupts per frame.
Additionally, on Amstrad Plus, we have multiple sources of interrupts as each DMA sound channel can trigger an interrupt.
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Note that:
* REPEAT Loops cannot be nested . Only one is allowed to be active per instruction stream at any time.
* REPEAT 0 and PAUSE 0 instructions have no effect, i.e. they are equivalent to NOP.
* Control group (4xxxh) instructions can be logically ORed to produce more complex instructions, e.g. INT|STOP = 4030h = Interrupt and Stop.
* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
A DMA control and status register (DCSR) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
* Bits2..0 are the channel enable bits. When set to "1" it enables the corresponding DMA channel. It can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on rest.
* Bits7..4 are the interrupt bits. An interrupt bit is set to "0" when the corresponding channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
* The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is active at "0" if at least one of the interrupt bits is "0".
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== Vectored Interrupt ==
The ASIC provides an interrupt vector on interrupt request.
The register IVR (at address 6805h) supplies the top 5 bits of the vector provided to the CPU. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt mode, always set up the IVR so that the top 5 bits are defined.
Bits2..1 of the IVR register are unused.
Bit0 of the IVR register controls whether DMA channel interrupts are automatically cleared.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
==== Interrupt Vector used on Z80 IM2 mode ====
{| class="wikitable"
|-
!Interrupt Vector
!Signal source
!Value
|-
|A15..A8||Z80||Register I
|-
|A7..A3||ASIC||IVR register bits7..3
|-
|A2..A1||ASIC||00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA raster
|-
|A0||ASIC||Always 0
|}
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