Additionally, on Amstrad Plus, we have multiple sources of interrupts as each DMA sound channel can trigger an interrupt.
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== Vectored Interrupt ==
In this mode, interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
The register IVR (at address 6805h) supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt, always set up the IVR so that the top 5 bits are defined.
Bit0 of the IVR controls whether DMA channel interrupts are automatically cleared.
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* The interrupt bits are set when a channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
* The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is "0" if at least one of the interrupt bits is "0".
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== Vectored Interrupt ==
In this mode, interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
The register IVR (at address 6805h) supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt, always set up the IVR so that the top 5 bits are defined.
Bit0 of the IVR controls whether DMA channel interrupts are automatically cleared.
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