Changes

FPGAmstrad

2 bytes added, 14:25, 18 September 2017

/* Some bad instruction timing analyses */

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| 02 || LD (BC),A || 2 || 2 || 3 || Normaly MEM_WR access is not prolongated.

This instruction ~~does~~ should certainly launch write since first step.

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| 10 || || 4/3 || 4/2 || 4/2

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