Changes
/* Instruction timing */ wikilink - todo: VHDL (and -blech!!!- verilog)-codes for 'strad Chips (Z80 family, AY/YM, ...)
=== Instruction timing ===
I tested instruction timing of [[T80 ]] compare to instruction timing of JavaCPC emulator. I deduce synchronization of Z80 with CRTC on M1 signal by WAIT_n insertion in order to have a multiple of 4 Tstates per instruction. I deduce also one WAIT_n inserted during MEM_WR operation (yes I log testbench T80, Iām crazy)
I just made a test bench log of T80 (log of instruction's M1, and first M1 coming after knowing that I send a lot of NOP after my instruction), and compare it to a JavaCPC timing array. Some instructions was not tested (interrupt wait, and special timing (instructions with change timing)), but all others passed correctly.
