Changes
/* Split Screen facility */
Three new memory mapped registers have been added within the ASIC, to provided a horizontally split screen facility. One at address 6801h defines the scan line after which the screen split occurs. A value of zero (as at power on reset) will turn this feature off.
The other register pair at 6802h and 6803h define the start address in memory (same number form as R12 and R13 respectively in the 6845, and therefore high byte first) which partly represents the location in memory from which to start displaying data for the lower screen (the full byte address is defined by the soft scroll register, 6845's internal scan counter and the split screen start address). This value is read when the 6845's Horizontal counter matches Horizontal Displayed (R1) on the line programmed it is then stored to be used on the next line.
Note that care should be taken with programming this facility such that the screen split does not alter the function of address bits A1-A8 and the dynamic memory refresh is not upset. This can be accomplished by setting the start of the second screen to lie on 16k boundary. The reason is that the dynamic memory refresh is derived from the memory address that the 6845 describes.
