Changes
/* Aleste ROMRAM prom (Gate Array 2, ROM/RAM enable) */
A7 RAMDIS ;-RAMDIS pin on expansion port
Outputs:
D0 BUFFER0 ? ;set LOW on read from even RAM address (16bit-to-8bit bus) D1 BUFFER1 ? ;set LOW on read from odd RAM address (16bit-to-8bit bus)
D2 /ROMEN ;ROM enable (note: ROMDIS is handled elsewhere)
D3 /RAMEN ;RAM enable
Page: 0000h 4000h 8000h C000h
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0000: B 6 B 6 6 6 6 6 6 6 6 6 B B 6 6 ;even addresses 0010: B 5 B 5 5 5 5 5 5 5 5 5 B B 5 5 ;odd addresses
0020: F F F F F F F F F F F F F F F F ;\inactive because /MREQ=high
0030: F F F F F F F F F F F F F F F F ;/
0070: F F F F F F F F F F F F F F F F ;/
0080: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;\
0090: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;same as above, but BUFFER0 and BUFFER1 bits all SET 00A0: F F F F F F F F F F F F F F F F ; similar to above(reading from internal RAM forcefully disabled via 00B0: F F F F F F F F F F F F F F F F ; (internal RAM forcefully disabled viaRAMDIS signal from expansion port) 00C0: F F F F F F F F F F F F F F F F ; RAMDIS signal from expansion port)(however WRITING to RAM isn't disabled, the "7" means 00D0: F F F F F F F F F F F F F F F F ; ... hmmsignal /RAMEN=LOW, he "B" and "7" values do what exactly ?so writing is possible)
00E0: F F F F F F F F F F F F F F F F ;
00F0: F F F F F F F F F F F F F F F F ;/
