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* [[CIO Registers (Summary)]]
* [[CIO Registers (Detailed)]]
The Zilog Z8536 CIO is a Counter and I/O chip.
== CPU Interface ==
The CPU accesses the CIO via four I/O ports: three Data ports, and one Control port, the latter one giving access to not less than 48 registers.
=== Data Ports ===
The First/Second Access Flipflop is TOGGLED on any write, and CLEARED on any read (ie. a dummy read can be used to force it to First Access state).
A special case is the reset feature: After setting register[00h].Bit0=1, the chip gets stuck in the 2nd Access phase, until one writes Bit0=0 in a 3rd access.
For details on the Registers, see [[CIO Registers (Summary)]], and [[CIO Registers (Detailed)]].
== Port A/B/C Features ==
