Changes
/* PWM Output */
== PWM Output ==
This image shows the PWM output. The PWM is clocked at 3.12MHz/2 (so one step is circa 630..640 µs).
* Normally, 7bit PWM should consist of one "packet" with 128 steps. However, this seems to be broken down to four "quarter-packets" with 32 steps. This technique reduces the PWM noise from 10kHz to in-audible 40kHz.
* The image shows one such "quarter-packet" with 32 steps (actually 33 steps, not sure why, so let's ignore that). Additionally, there are some dummy steps with constant LOW level inserted between each quarter-packet, making each quarter 39 steps long. This is done to achieve a sample rate of 10kHz (a full packet is 156 = 4*39 steps, so sample rate is 3.12MHz/2/156 = 10kHz).
* For whatever reason, the quarter packers aren't always 39 steps long, and instead they vary from 38 to 40 steps. Anyways, better let's ignore that, too.
[[File:SP0256 PWM Output.png]]
