Changes

== Envelope Shape/Cycle Control Register (R15) ==

Registers R16 and R17 function as intermediate data storage registers between the PSG/CPU data bus (DA0--DA7) and the two I/O ports (IOA7--IOA0 and IOB7--IOB0). Both ports are available in the AY-3-8910; only I/O port A is available in the AY-3-8912; none are available on the AY-3-8913. Using registers R16 and R17 for the transfer of I/O data has no effect on sound generation.

Since the primary use of the PSG is to produce sound for the highly imperfect amplitude detection mechanism of the human ear, the D/A conversion is performed in logarithmic steps with a normalized voltage range of from 0 to 1 Volt. The specific amplitude control of each of the three D/A Converters is acomplished by the three sets of 4-bit outputs of the Amplitude Control block, while the Mixer outputs provide the base signal frequency (Noise and/or Tone).

Fig 2. DETAIL OF TWO CYCLES Of Fig 1 (ref. waveform "1010" in Fig.1)

Fig 3. D/A CONVERTER OUTPUT

Fig 4. SINGLE TONE WITH ENVELOPE SHAPE/CYCLE PATTERN 1010

Fig 5. MIXTURE OF THREE TONES WITH FIXED AMPLITUDE

Maximum Ratings*

Storage Temperature ...... -55°C to +150°C

Operating Temperature ...... 0°C to 40°C

Vcc and all other input/Output Voltages with Respect to Vss ...... -0.3V to +8.0V

Storage Conditions (unless otherwise noted):

Vcc = ± 5V ±5%

Vss = GND

Operating Temperature = 0°C to +40°C

Characteristics Sym Min Typ** Max Units Conditions

DC CHARACTERISTICS

All inputs

Low level Vil 0 - 0.6 V

High level Vih 2.4 - Vcc V

All Outputs (except Analog Channel Outputs

Low level Vol 0 - 0.5 V Iol = 1.6mA, 20pF

High level Voh 2.4 - Vcc V Ioh = 100uA, 20pF

Analog Channel Outputs Vo 0 - 60 dB Test Curcuit: Fig 6

Power Supply Current Icc - 45 85 mA

AC CHARACTERISTICS

Clock Input Fig 7.

Frequency fc 1 - 2 MHz

Rise Time tr - - 50 ns

Fall Time tf - - 50 ns

Duty Cycle - 25 50 85 %

Bus Signals (BDIR,BC2,BC1)

Associative Delay Time tao - - 50 ns

Reset Fig. 8

Reset Pulse Width trw 500 - - ns

Reset to Bus Control Delay Time trb 100 - - ns

A9, A8, DA7--DA0 (Address Mode) Fig 9

Address Setup Time tas 400 - - ns

Address Hold Time tah 100 - - ns

DA7--DA0 (Write Mode) Fig. 10

Write Data Pulse Width tdw 500 - 10,000 ns

Write Data Setup Time tds 50 - - ns

Write Data Hold Time tdh 100 - - ns

DA7--DA0 (Read Mode) Fig. 11

Read Data Access Time tda - 250 500 ns

DA7--DA0 (Inactive Mode)

Tristate Delay Time tts - 100 200 ns

** Typical values are at ±25°C and nominal voltages

Maximum Ratings*

Storage Temperature ...... -55°C to +150°C

Operating Temperature ...... 0°C to 70°C

Vcc and all other input/Output Voltages with Respect to Vss ...... -0.3V to +8.0V

* Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and functional operation of the devices at these conditions is not implied -- operating ranges are specified in Standard Conditions. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data labelled " typical" is presented for design guidance only and is not guaranteed.

Storage Conditions (unless otherwise noted):

Vcc = ± 5V ±5%

Vss = GND

Operating Temperature = 0°C to +70°C

Characteristics Min Sym Max Units Conditions

DC CHARACTERISTICS

All inputs

Low level Vil 0 0.7 V

High level Vih 2.2 Vcc V

All Outputs (except Analog Channel Outputs

Low level Vol 0 0.4 V 1 TTL Load

High level Voh 2.4 Vcc V +100pf

Analog Channel Outputs Vo 0 2000 uA Test Curcuit: Fig 6

Power Supply Current Icc - 85 mA

AC CHARACTERISTICS

Clock Input Fig 7.

Frequency fc 1 2.5 MHz

Rise Time tr - 50 ns

Fall Time tf - 50 ns

Duty Cycle - 40 60 %

Bus Signals (BDIR,BC2,BC1)

Associative Delay Time tao - 50 ns

Reset Fig. 8

Reset Pulse Width trw 5 - us

Reset to Bus Control Delay Time trb 100 - ns

A9, A8, DA7--DA0 (Address Mode) Fig 9

Address Setup Time tas 300 - ns

Address Hold Time tah 50 - ns

DA7--DA0 (Write Mode) Fig. 10

Write Data Pulse Width tdw 1800 - ns

Write Data Setup Time tds 50 - ns

Write Data Hold Time tdh 100 - ns

DA7--DA0 (Read Mode) Fig. 11

Read Data Access Time tda - 350 ns

DA7--DA0 (Inactive Mode)

Tristate Delay Time tts - 400 ns

Fig 7. CLOCK AND BUS SIGNAL TIMING

Fig 8. RESET TIMING

Fig 9. LATCH ADDRESS TIMING

Fig 10. WRITE DATA TIMING

Fig 11. READ DATA TIMING