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KC Compact Computer

4,164 bytes removed, 16:06, 13 March 2007
/* Z8536 CIO */
=== Z8536 CIO ===
The Z8536 CIO chip is a counter and I/O chip. In the KC compact system it is used to generate interrupts, access to the parallel printer port, and possibly video control.
 
When b12 of the I/O address is "0", the Z8536 is selected.
 
Bit b9 and b8 of the I/O address select the registers of the Z8536:
 
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b9''||''b8''||''Register''
|-
|0||0||Port B data register
|-
|0||1||Port C data register
|-
|1||0||Control register
|-
|1||1||Port A data register)
|-
|}
 
(note: b8 is passed through an inverter and this describes the order of the registers in the table compared to the order of the registers in the z8536 datasheet)
 
To avoid conflict with other peripherals the Z8536 should be access using:
 
Port address Register
&ECxx Port B data register
&EDxx Port C data register
&EExx control registers
&EFxx Port A data register
 
In the KC Compact:
 
* Port A is setup as I/O and is connected to the parallel printer port
* Port B is setup as timer and is connected to the video hardware (?)
* Port C is setup as timer and is connected to the Interrupt hardware
 
On start-up, the KC compact programs the z8536 to the following state:
 
* Port A: I/O mode: all bits are set to output, and bit 7 is inverted when writing. (bit 7 is /strobe signal to printer)
* Port B: Counter mode (port B is split into two counters, both are setup the same): continuous count, restarts when count is over, uses external trigger, uses external input to update count, pulse output (when count is over)
 
* Port C: Counter mode: same configuration as port B.
 
Port C is used to generate interrupts. The counter input is HSYNC (the counter counts counter-input transitions; low-high and high-low). The trigger input is VSYV (this signal is derived from VSYNC).
 
What this means:
 
* The Z8536 Port C counter is updated when HSYNC changes state
* The Z8536 Port C counter is reset when VSYV changes state
 
With the default settings, the Z8536 will count 26 HSYNC transitions (52 lines of the display covered in this time) and generate a interrupt. At VSYNC the counter is reset so that the interrupts are synchronised.
 
I do not know the exact function of the counter's of Port B. I have looked at the schematics, and it appears to control the video hardware. Maybe the KC compact has a programmable pixel clock, if it does, then the base resolution can be changed.
 
CPC Interrupts:
 
* synchronised to 2 HSYNCs after VSYNC
* interrupts cannot be generated closer than 32 lines
* counter inside Gate Array counts up to 52 lines.
* interrupt can be cleared by writing to bit 4 of Mode/ROM register in Gate Array (counter is also reset at this time)
 
KC compact interrupts:
 
* interrupt can be cleared by writing to bit 4 of Mode/ROM register at 0x07fxx (counter is *not* reset at this time)
* interrupt system fully programmable: can count HSYNCS, or count internal Z8536 clocks!
 
Therefore, the KC compact interrupt system is more powerful than the CPC!
TEST feature
When the KC compact is reset, the /TEST signal on the expansion port is checked.
 
If it is high (1), the operating system will startup and BASIC will be entered. If it is low (0), the KC compact will enter a data transfer sequence using DATA2, DATA1, /STROBE and DATA7 on the expansion connector.
 
Data transfer:
 
The data transfer is controlled by another computer, the KC compact is the "slave".
 
Using DATA2, DATA1, /STROBE and DATA7, a program of 256 bytes in size can be transfered into KC compact memory at &a880. When all bytes have been transfered, this program will be executed.
 
KCC Side:
Synchronisation stage (Data transfer begin) /STROBE must read as "1"!!
wait for DATA1 to change from "1"to "0".
Synchronisation Acknowledge stage write 0x0f: DATA2="1",DATA7="0".
Data transfer stage (repeat for 256 bytes) Data byte transfer repeat 8 times (once for each data bit)
 
* write 0x0ff: DATA2="1",DATA7="1", and wait for /STROBE to read as "1"
* read inputs: DATA1=data bit
 
Data byte acknowledge stage write: 0x0f0: DATA2="0", DATA7="1", and wait for /STROBE to read as "1"
 
* /STROBE and DATA1 are inputs
* DATA2 and DATA7 are outputs
== Connecting a KC compact to a CPC+ monitor ==
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