Changes
CRTC
,/* VSYNC */
On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.
=== Mid-PPI VSYNC ===
In the CRTC Compendium, chapter 7.3 "Fake VSYNC", [[Longshot]] has also experimented with reversing the direction of PPI port B to output a VSYNC signal from the PPI to the Gate Array. This technique is not for the faint of heart! As an exception, on CRTCs 3/4, if R7=0 then mid-the Ghost VSYNC will instead occur on of CRTC 2 overpowers the odd fieldPPI VSYNC.
=== Subpixel vertical hardware scroll ===
By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated [https://youtu.be/bSjRU6Wye00 vertical hardware scroll] with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU.
=== PPI Mid-VSYNC ===
On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pin of pulse starts in the CRTC is directly connected to bit0 of port B middle of the PPI. There is no delay involvedraster line, at HCC=R0/2.
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