Changes
CRTC
,/* VSYNC */
On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.
On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.
On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.
=== PPI VSYNC ===
The VSYNC pin of the CRTC is directly connected to Bit0 of port B of the PPI. There is no delay involved.
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