Changes
CRTC
,/* HSYNC and VSYNC */
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== HSYNC and VSYNC ==
The HSYNC and VSYNC signals signal from the CRTC are is not directly connected to the display. They are It is passed to the [[Gate Array]] for further modification. See its wiki page.
While HSYNC and VSYNC are is active, all the CRTC counters continue to increment normally and addresses continue to be generated.
On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC. Similarly, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC. <br> === HSYNC ===
The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed then no HSYNC is generated (and therefore, no interrupts). On CRTCs 2/3/4, if 0 is programmed then this gives an HSYNC width of 16.
On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped.
On CRTCs 1/2/3/4, HSYNCs can be contiguous.
On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.
So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4.
On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse.
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Bit0 of port B of the PPI is directly connected to the VSYNC pin of the CRTC.
On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.
On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.
On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.
