Changes
6502
,All I/O operations are memory-mapped. There are no port-based I/O instructions.
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== Half Cycles ==
The 6502 divides each clock cycle into two phases (ϕ1 and ϕ2):
* During the ϕ1 half-cycle, no bus access occurs. This phase is dedicated to internal CPU operations.
* During the ϕ2 half-cycle, the CPU accesses the external bus for memory reads/writes or I/O operations.
The use of half-cycles ensures that memory and I/O devices have predictable timing windows when the CPU will access the bus, while still allowing the CPU to perform internal operations in parallel.
Unlike most microprocessors, the 6502 does not make memory accesses on an "as needed" basis. It always does a fetch or store on every single clock cycle. When there isn't anything to be fetched or stored, a "garbage" fetch or store occurs. This is mainly of importance with the memory-mapped I/O devices:
* On NMOS, when adding a carry to the MSB of an address, a fetch occurs at a garbage address. On CMOS, the last byte of the instruction is refetched.
* On NMOS, when doing a fetch-modify-store instruction (INC, DEC, ASL, LSR, ROL, ROR), garbage is stored into the location during the "modify" cycle... followed by the "real" store cycle which stores the correct data. On CMOS, a second fetch is performed instead of a garbage store.
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On NMOS, the simultaneous assertion of a hardware interrupt line and execution of BRK was not accounted for in the design — the BRK instruction will be ignored in such a case. On CMOS, this situation is correctly handled by executing BRK and then servicing the interrupt.
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