Changes
/* Interrupt management */
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
An interruption occurs at the end of an HSYNC. On CRTCs 3/4, the HSYNC occurs 1µs later than on CRTCs 0/1/2.
Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.
