Changes

* See the document "Extra CPC Plus Hardware Information" for more details.

=== Horizontal and Vertical Sync (R3) ===

*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.

*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

=== Interlace and Skew (R8) ===

* In interlace sync and video mode, alternating lines are displayed in the even and odd field to double the resolution. In this mode, it is necessary to reprogram the CRTC as if we were building a frame of 624 lines. The 625th line is managed automatically by the CRTC

[[File:CRTC Interlace modes.png]]

=== R31 on Type 1 ===

R31 doesn't exist on types 0,2,3,4.

=== R12/R13 on Type 1 ===

In demos to make a display compatible with all CRTCs, program R12/R13 when VCC!=0. This will then take effect at the next frame start.

=== Status register on Type 1 ===

All the other bits read as 0 and don't have any function.

=== R10/R11 on ASIC/Pre-ASIC ===

|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)

|}

=== Reading from CRTC registers on ASIC/Pre-ASIC ===