Changes
/* CSYNC signal */
If a video mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the video mode.
The HSYNC is modified before being sent to the monitor. It happens 2µs after activation of the CRTC HSYNC from the CRTC and stay a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).
For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 included.
The same logic applies to VSYNC is also modified before being sent to the monitor. It happens 2 with lines* after the VSYNC from the CRTC and stay a maximum instead of 2 lines (same cut rule if VSYNC is greater than 4). PAL (50Hz) does need two lines VSYNC_width, and 4µs HSYNC_widthchars. The Gate Array VSYNC is considered complete when the 26th line has been processed. Then the Gate Array stops outputting the palette colour black.
The Gate Array uses 2 internal counters to create its CSYNC signal:
* H06 which counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the CSYNC signal when H06 reaches 2. It deactivates this signal when H06 reaches 6.* V26 which counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the CSYNC signal when V26 reaches 2. It deactivates this signal when V26 reaches 6.
On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array.
The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.
The CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.
== Controlling the Gate Array ==
