Changes
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
== HSYNC and VSYNC ==
The Gate Array has 2 other internal counters that are used to create its CSYNC signal:
* H06 which counts the number of CRTC characters during an HSYNC
* V26 which counts the number of HSYNCs during a VSYNC
== Controlling the Gate Array ==
