Changes
/* Reset */
=== Reset ===
The following has been tested using the "software reset" which is triggered through the control port.
* After reset (including software reset using the control port), rest all registers are reset to 0. In addition the selected register (port 4) is set to 0 and read and write increment are not inhibited.
* The elected register (port 4) is set to 0 and port read and write increment is not inhibited. * If using software reset and the reset is held, using the "software reset" then reading or writing to the vram VRAM data port will cause the CPC to hang. I believe it's the V9990 is continuously asserting /WAIT but I can't confirmthrough code.
* Reset will stop any commands in progress and will clear pending interrupts.
* If reset is held: 3,4,7,8,9,10,11,12,13,14 and 15 reads databus, port 1 reads 0, port 5 and 6 read status,
=== Coordinates ===
