Changes
/* Technical */
3) In bitmap mode width (XIMM) and bpp (CLRM) settings are used. HSCN and C25M are ignored. Therefore logical vram address of Y is defined as: XIMM/4 when 2bpp, XIMM/2 when 4bpp, XIMM when 8bpp and XIMM*2 when 16bpp.
4) For the command-engine, standby mode is identical in operation to the bitmap mode.
* PSET command:
The logical vram address that is modified is based on the mode. See above.
The bit pattern written depends on the CLRM.
e.g.
foreground is set to &ffff.
y=0
P1 and 2bpp:
x=0 ->logical VRAM address=0, data = C0
x=1 ->logical VRAM address=0, data = 0C
x=2 ->logical VRAM address=1, data = C0
x=3 ->logical VRAM address=1, data = 0C
etc.
P1 and 4bpp:
x=0 ->logical VRAM address=0, data = F0
x=1 ->logical VRAM address=0, data = 0F
x=2 ->logical VRAM address=1, data = F0
x=3 ->logical VRAM address=1, data = 0F
etc.
P1 and 8bpp:
x=0 ->logical VRAM address=0, data = FF
x=1 ->logical VRAM address=0, data = FF
x=2 ->logical VRAM address=1, data = FF
x=3 ->logical VRAM address=1, data = FF
etc.
P1 and 16bpp:
x=0 ->logical VRAM address=0, data = FF
x=1 ->logical VRAM address=0, data = FF
x=2 ->logical VRAM address=1, data = FF
x=3 ->logical VRAM address=1, data = FF
etc.
bitmap and 2bpp:
x=0 ->logical VRAM address=0, data=c0
x=1 ->logical VRAM address=0, data=30
x=2 ->logical VRAM address=0, data=0c
x=3 ->logical VRAM address=0, data=03
bitmap and 4bpp:
x=0 ->logical VRAM address=0, data=f0
x=1 ->logical VRAM address=0, data=0f
x=2 ->logical VRAM address=1, data=f0
x=3 ->logical VRAM address=1, data=0f
bitmap and 8bpp:
x=0 ->logical VRAM address=0, data=ff
x=1 ->logical VRAM address=1, data=ff
x=2 ->logical VRAM address=2, data=ff
x=3 ->logical VRAM address=3, data=ff
bitmap and 16bpp:
x=0 ->logical VRAM address=0,1 data=ffff
x=1 ->logical VRAM address=2,3, data=ffff
x=2 ->logical VRAM address=4,5 data=ffff
x=3 ->logical VRAM address=6,7 data=ffff
(standby is the same as bitmap)
[[Category:Hardware]]
