Changes
/* Data separator syncing */
The pre-amble is 12 bytes of 0 which are used to prime and synchronize the data separator with the data bits and clock bits.
0 encodes as AAAA and has clock bits of '1' and data bits of '0' interleaved. The data separator expects a continuous stream of 0 bits to sync and maintains a count of them. If the separator sees a 1 data bit during this time then it will re-sync and reset it's internal count to 0. When a certain count is reached then the data separator is synced and it will output separate clocks and data to the FDC. Amstrad uses these data separators:* SED9420C* FDC9216 These differ in the number of bits required for sync.
===FDC syncing and Address Mark ===
